TEXAS INSTRUMENTS CDC318A Technical data

查询CDC318A供应商

CDC318A

1-LINE TO 18-LINE CLOCK DRIVER

WITH I

2

C CONTROL INTERFACE

SCAS614 – SEPTEMBER 1998

D

High-Speed, Low-Skew 1-to-18 Clock Buffer
for Synchronous DRAM (SDRAM) Clock

DL PACKAGE

(TOP VIEW)

Buffering Applications

1

48

D

Output Skew, t

D

Pulse Skew, t

D

Supports up to Four Unbuffered SDRAM

, Less Than 250 ps

sk(o)

, Less Than 500 ps

sk(p)

Dual Inline Memory Modules (DIMMs)

D

I2C Serial Interface Provides Individual
Enable Control for Each Output

D

Operates at 3.3 V

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

100-MHz Operation

D

ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015

D

Packaged in 48-Pin Shrink Small Outline
(DL) Package

description

The CDC318A is a high-performance clock buffer
designed to distribute high-speed clocks in PC
applications. This device distributes one input (A)
to 18 outputs (Y) with minimum skew for clock
distribution. The CDC318A operates from a 3.3-V
power supply. It is characterized for operation
from 0°C to 70°C.

NC

2

NC

3

V

CC

4

1Y0

5

1Y1

6

GND

7

V

CC

8

1Y2
1Y3

9

GND

10

A

11

V

12

CC

2Y0

13

2Y1

14

GND

15

V

16

CC

2Y2

17

2Y3

18

GND

19

V

20

CC

5Y0

21

GND

22

V

23

CC

SDATA

NC – No internal connection

24

47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25

NC
NC
V

CC

4Y3
4Y2
GND
V

CC

4Y1
4Y0
GND
OE
V

CC

3Y3
3Y2
GND
V

CC

3Y1
3Y0
GND
V

CC

5Y1
GND
GND
SCLOCK

This device has been designed with consideration
for optimized EMI performance. Depending on the
application layout, damping resistors in series to
the clock outputs (like proposed in the PC100
specification) may not be needed in most cases.

The device provides a standard mode (100K-bits/s) I
is as a slave/receiver. The device address is specified in the I

2

C serial interface for device control. The implementation

2

C device address table. Both of the I2C inputs

(SDATA and SCLOCK) are 5-V tolerant and provide integrated pullup resistors (typically 140 kΩ).
Three 8-bit I

2

C registers provide individual enable control for each of the outputs. All outputs default to enabled
at powerup. Each output can be placed in a disabled mode with a low-level output when a low-level control bit
is written to the control register. The registers are write only and must be accessed in sequential order (i.e.,
random access of the registers is not supported).

The CDC318A provides 3-state outputs for testing and debugging purposes. The outputs can be placed in a
high-impedance state via the output-enable (OE) input. When OE is high, all outputs are in the operational state.
When OE is low, the outputs are placed in a high-impedance state. OE provides an integrated pullup resistor.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Intel is a trademark of Intel Corporation

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1998, Texas Instruments Incorporated

1

CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I

SCAS614 – SEPTEMBER 1998

logic diagram (positive logic)

2

C CONTROL INTERFACE

INPUTS

OE A 1Y0–1Y3 2Y0–2Y3 3Y0–3Y3 4Y0–4Y3 5Y0–5Y1

L X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z
H L L L L L L
H H H

†

The function table assumes that all outputs are enabled via the appropriate I2C configuration register bit. If the output is disabled
via the appropriate configuration bit, then the output is driven to a low state, regardless of the state of the A input.

38

OE

†

FUNCTION TABLE

†

H

OUTPUTS

†

H

†

H

†

H

SDATA

SCLOCK

24

I2C

I2C

25

11

A

Register

Space

18

/

4, 5, 8, 9

13, 14, 17, 18

31, 32, 35, 36

40, 41, 44, 45

21, 28

1Y0–1Y3

2Y0–2Y3

3Y0–3Y3

4Y0–4Y3

5Y0–5Y1

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

Terminal Functions

TERMINAL

NAME NO.

1Y0–1Y3 4, 5, 8, 9 O 3.3-V SDRAM byte 0 clock outputs
2Y0–2Y3
3Y0–3Y3
4Y0–4Y3
5Y0–5Y1

A

OE

SCLOCK

SDATA

GND

NC

V

CC

13, 14, 17, 18 O 3.3-V SDRAM byte 1 clock outputs
31, 32, 35, 36 O 3.3-V SDRAM byte 2 clock outputs
40, 41, 44, 45 O 3.3-V SDRAM byte 3 clock outputs

21, 28 O 3.3-V clock outputs provided for feedback control of external phase-locked loops (PLLs)

11 I Clock input
38 I
25 I I2C serial clock input. A nominal 140-kΩ pullup resistor is internally integrated.
24 I/O

6, 10, 15, 19, 22, 26,

27, 30, 34, 39, 43

1, 2, 47, 48 No internal connection. Reserved for future use.

3, 7, 12, 16, 20, 23,

29, 33, 37, 42, 46

Output enable. When asserted, OE puts all outputs in a high-impedance state. A nominal
140-kΩ pullup resistor is internally integrated.

Bidirectional I2C serial data input/output. A nominal 140-kΩ pullup resistor is internally
integrated.

Ground

3.3-V power supply

CDC318A

1-LINE TO 18-LINE CLOCK DRIVER

WITH I

2

C CONTROL INTERFACE

SCAS614 – SEPTEMBER 1998

I2C DEVICE ADDRESS

A7

A6 A5 A4 A3 A2 A1 A0 (R/W)

H H L H L L H —

I2C BYTE 0-BIT DEFINITION

BIT

7 2Y3 enable (pin 18) H
6 2Y2 enable (pin 17) H
5 2Y1 enable (pin 14) H
4 2Y0 enable (pin 13) H
3 1Y3 enable (pin 9) H
2 1Y2 enable (pin 8) H
1 1Y1 enable (pin 5) H
0 1Y0 enable (pin 4) H

†

When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.

DEFINITION DEFAULT VALUE

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDC318A
1-LINE TO 18-LINE CLOCK DRIVER
WITH I

SCAS614 – SEPTEMBER 1998

2

C CONTROL INTERFACE

I2C BYTE 1-BIT DEFINITION

BIT

7 4Y3 enable (pin 45) H
6 4Y2 enable (pin 44) H
5 4Y1 enable (pin 41) H
4 4Y0 enable (pin 40) H
3 3Y3 enable (pin 36) H
2 3Y2 enable (pin 35) H
1 3Y1 enable (pin 32) H
0 3Y0 enable (pin 31) H

†

When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.

BIT

7 5Y1 enable (pin 28) H
6 5Y0 enable (pin 21) H
5 Reserved H
4 Reserved H
3 Reserved H
2 Reserved H
1 Reserved H
0 Reserved H

†

When the value of the bit is high, the output is enabled.
When the value of the bit is low, the output is forced to a
low state. The default value of all bits is high.

DEFINITION DEFAULT VALUE

I2C BYTE 2-BIT DEFINITION

DEFINITION DEFAULT VALUE

†

†

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265