TEXAS INSTRUMENTS CDC305 Technical data
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CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
D
Replaces SN74AS305
D
Maximum Output Skew of 1 ns
D
Maximum Pulse Skew of 1ns
D
TTL-Compatible Inputs and Outputs
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
1
Q3
2
Q4
GND
GND
GND
3
4
5
6
Q
5
7
6
Q
8
Q
7
16
15
14
13
12
11
10
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
Q8
9
description
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters t
when a divide-by-two function is required.
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR PRE CLK Q1–Q4 Q5–Q8
L H X L H
H LX H L
L LXL†L
H HLQ0Q
H H ↑ Q
†
This configuration does not persist when
PRE
or CLR returns to its inactive (high)
level.
sk(o)
and t
sk(p)
OUTPUTS
0
to ensure performance as a clock driver
†
0
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
PRE
CLK
14
10
11
S
R
C1
logic diagram (positive logic)
15
16
15
16
Q1
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
Q7
9
Q8
Q1
Q2
1
10
PRE
CLK
CLR
11
14
S
C1
R
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage, V
Input voltage, V
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
Q3
2
Q4
6
5
Q
7
Q6
8
Q7
9
Q8
‡
Maximum power dissipation at TA = 55°C (in still air) (see Note 1):D package 0.77 W. . . . . . . . . . . . . . . . . .
N package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
‡
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
application note in the 1994
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
ABT Advanced BiCMOS Technology Data Book
, literature number SCBD002B.
Package Thermal Considerations
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
T
A
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –24 mA
Low-level output current 48 mA
Operating free-air temperature 0 70 °C
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
V
I
I
I
I
I
IK
OH
OL
I
IH
IL
O
CC
‡
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2
VCC = 4.5 V, IOH = –24 mA 2 2.8
VCC = 4.5 V, IOL = 48 mA 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.5 mA
VCC = 5.5 V, VO = 2.25 V –50 –150 mA
VCC = 5.5 V, See Note 2 40 70 mA
grounded, then with CLK and CLR grounded.
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
f
clock
t
w
t
su
Clock frequency 0 80 MHz
CLR or PRE low 5
Pulse duration
Setup time before CLK↑ CLR or PRE inactive 6 ns
CLK high
CLK low 6
4
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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