Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
1
Q3
2
Q4
GND
GND
GND
3
4
5
6
Q
5
7
6
Q
8
Q
7
16
15
14
13
12
11
10
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
Q8
9
description
The CDC305 contains eight flip-flops designed to have low skew between outputs. The eight outputs (four
in-phase with CLK and four out-of-phase) toggle on successive CLK pulses. Preset (PRE) and clear (CLR)
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC305 has output and pulse-skew parameters t
when a divide-by-two function is required.
The CDC305 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLRPRECLKQ1–Q4 Q5–Q8
LHXLH
HLX H L
LLXL†L
HHLQ0Q
HH↑Q
†
This configuration does not persist when
PRE
or CLR returns to its inactive (high)
level.
sk(o)
and t
sk(p)
OUTPUTS
0
to ensure performance as a clock driver
†
0
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1995, Texas Instruments Incorporated
1
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
logic symbol
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
†
CLR
PRE
CLK
14
10
11
S
R
C1
logic diagram (positive logic)
15
16
15
16
Q1
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
Q7
9
Q8
Q1
Q2
1
10
PRE
CLK
CLR
11
14
S
C1
R
1D
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
application note in the 1994
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MINMAXUNIT
f
clock
t
w
t
su
Clock frequency080MHz
CLR or PRE low5
Pulse duration
Setup time before CLK↑CLR or PRE inactive6ns
CLK high
CLK low6
4
ns
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC305
CLK
Q, Q
R
500 Ω
C
pF
ns
PRE
CLR
Q, Q
R
500 Ω
C
50 pF
ns
()
See Figure 2
t
CLK
R
500 Ω
C
pF
ns
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature (unless otherwise noted) (see Figure 1)
PARAMETER
‡
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
sk(p)
t
r
t
†
‡
f
All typical values are at VCC = 5 V, TA = 25°C.
f
minimum values are at CL = 0 to 30 pF.
max
FROM
(INPUT)
or
CLK
TO
(OUTPUT)
Q
Q
Q1–Q8
Q1, Q8
Q2–Q7
TEST CONDITIONSMIN TYP†MAXUNIT
80MHz
=
L
=
L
RL = 500 Ω,
=
L
,
,
,
p
= 50
L
p
=
L
CL = 10 pF to 30 pF,
p
= 10 pF to 30
L
p
269
269
3712
3712
1
ns
1
1.5
1.5
2
4.5ns
3.5ns
CLR
PRE
CLK
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
R
C
(see Note A)
or
t
w
Q
1.3 V
t
su
1.3 V
L
LOAD CIRCUIT
t
PLH
1.3 V1.3 V
L
Test Point
1.3 V
t
PHL
3.5 V
0.3 V
3.5 V
0.3 V
V
OH
V
OL
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC305
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS326A – JUNE 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
CLR, PRE
0
CLK
t
PHL1
Q1
t
PLH1
Q2
Q3
Q4
Q
Q
Q
t
PLH2
t
PLH3
t
PLH4
t
PHL5
5
t
PHL6
6
t
PHL7
7
t
PHL8
t
PLH5
t
PLH6
t
PLH7
t
PLH8
t
PHL2
t
PHL3
t
PHL4
NOTES: A. t
B. t
C. t
D. t
8
Q
CLK to Q are calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
CLK to Q are calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
CLK to Q and Q
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
is calculated as the greater of | t
sk(p)
are calculated as the greater of:
– t
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(n = 1, 2, 3, 4)
PLHn
(n = 1, 2, 3, 4)
PHLn
(n = 5, 6, 7, 8)
PLHn
(n = 5, 6, 7, 8)
PHLn
(n = 1, 2, 3, 4), t
PLHn
(n = 1, 2, 3, 4), t
PHLn
| (n = 1, 2, 3, ..., 8).
sk(o)
(n = 5, 6, 7, 8)
PHLn
(n = 5, 6, 7, 8)
PLHn
and t
sk(p)
5
PACKAGE OPTION ADDENDUM
www.ti.com
30-Mar-2005
PACKAGING INFORMATION
Orderable DeviceStatus
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
CDC305-1NOBSOLETEPDIPN16TBDCall TICall TI
CDC305DOBSOLETESOICD16TBDCall TICall TI
CDC305DROBSOLETESOICD16TBDCall TICall TI
CDC305NOBSOLETEPDIPN16TBDCall TICall TI
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(2)
Lead/Ball Finish MSL Peak Temp
(3)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is
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In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI
to Customer on an annual basis.
Addendum-Page 1
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