TEXAS INSTRUMENTS CDC304 Technical data
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CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
D
Replaces SN74AS304
D
Maximum Output Skew of 1 ns
D
Maximum Pulse Skew of 1.5 ns
D
TTL-Compatible Inputs and Outputs
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
D OR N PACKAGE
(TOP VIEW)
1
Q3
2
Q4
Q5
Q6
Q7
3
4
5
6
7
8
GND
GND
GND
16
15
14
13
12
11
10
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
9
Q8
description
The CDC304 contains eight flip-flops designed to have low skew between outputs. The eight outputs (in-phase
with CLK) toggle on successive CLK pulses. Preset (PRE) and clear (CLR) inputs are provided to set the Q
outputs high or low independent of the clock (CLK) input.
The CDC304 has output and pulse-skew parameters t
when a divide-by-two function is required.
The CDC304 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR PRE CLK
L H X L
H LX H
L LX L
H H ↑ Q
H H L Q
†
This configuration does not persist
when PRE
inactive (high) level.
or CLR returns to its
sk(o)
and t
sk(p)
OUTPUTS
Q1–Q8
†
0
0
to ensure performance as a clock driver
logic symbol
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
‡
10
PRE
11
CLK
14
CLR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S
T
R
15
Q1
16
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
Q7
9
Q8
Copyright 1995, Texas Instruments Incorporated
1
CDC304
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS325A – JULY 1990 – REVISED NOVEMBER 1995
logic diagram (positive logic)
10
PRE
CLK
CLR
11
14
S
C1
R
1D
15
16
Q1
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
Q7
9
Q8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 1):D package 0.77 W. . . . . . . . . . . . . . . . . .
N package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
application note in the 1994
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
ABT Advanced BiCMOS Technology Data Book
, literature number SCBD002B.
Package Thermal Considerations
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
T
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –24 mA
Low-level output current 48 mA
Input clock frequency 80 MHz
Operating free-air temperature 0 70 °C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
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