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CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
D
Replaces SN74AS303
D
Maximum Output Skew Between Same
D OR N PACKAGE
(TOP VIEW)
Phase Outputs of 1 ns
1
16
D
Maximum Pulse Skew of 1 ns
D
TTL-Compatible Inputs and Outputs
D
Center-Pin VCC and GND Configurations
Minimize High-Speed Switching Noise
D
Package Options Include Plastic
Small-Outline (D) Package and Standard
Plastic (N) 300-mil DIPs
Q3
Q4
GND
GND
GND
Q5
Q6
Q
2
3
4
5
6
7
8
7
15
14
13
12
11
10
Q2
Q1
CLR
V
CC
V
CC
CLK
PRE
9
Q8
description
The CDC303 contains eight flip-flops designed to have low skew between outputs. The eight outputs (six
in-phase with CLK and two out-of-phase) toggle on successive CLK pulses. Preset (PRE
inputs are provided to set the Q and Q outputs high or low independent of the clock (CLK) input.
The CDC303 has output and pulse-skew parameters t
sk(o)
and t
to ensure performance as a clock driver
sk(p)
when a divide-by-two function is required.
The CDC303 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLR PRE CLK Q1–Q6 Q7–Q8
L H X L H
H LX H L
L LXL†L
H H ↑ Q
H H L Q
†
This configuration does not persist when
PRE
or CLR returns to its inactive (high)
level.
OUTPUTS
0
0
†
Q
0
Q
0
) and clear (CLR)
logic symbol
‡
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
‡
10
PRE
11
CLK
14
CLR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
S
T
R
15
Q1
16
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
7
Q
9
Q8
Copyright 1995, Texas Instruments Incorporated
1
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
logic diagram (positive logic)
10
PRE
CLK
CLR
11
14
S
C1
R
1D
15
16
Q1
Q2
1
Q3
2
Q4
6
Q5
7
Q6
8
7
Q
9
8
Q
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage, VCC 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage, VI 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at T
= 55°C (in still air) (see Note 1):D package 0.77 W. . . . . . . . . . . . . . . . . .
A
N package 1.2 W. . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTE 1: The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 300 mils,
except for the N package, which has a trace length of zero. For more information, refer to the
application note in the 1994
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
ABT Advanced BiCMOS Technology Data Book
, literature number SCBD002B.
Package Thermal Considerations
recommended operating conditions
MIN NOM MAX UNIT
V
CC
V
IH
V
IL
I
OH
I
OL
f
clock
T
A
Supply voltage 4.5 5 5.5 V
High-level input voltage 2 V
Low-level input voltage 0.8 V
High-level output current –24 mA
Low-level output current 48 mA
Input clock frequency 80 MHz
Operating free-air temperature 0 70 °C
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
V
V
CLK
Q, Q
R
500 Ω
C
50 pF
ns
PRE
CLR
Q, Q
R
500 Ω
C
pF
ns
()
See Figure 2
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP†MAX UNIT
V
IK
OH
V
OL
I
I
I
IH
I
IL
‡
I
O
I
†
All typical values are at VCC = 5 V, TA = 25°C.
‡
The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS.
NOTE 2: ICC is measured with CLK and PRE
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
f
clock
t
w
t
su
Clock frequency 0 80 MHz
Pulse duration
Setup time before CLK↑ CLR or PRE inactive 6 ns
VCC = 4.5 V, II = –18 mA –1.2 V
VCC = 4.5 V to 5.5 V, IOH = –2 mA VCC–2
VCC = 4.5 V, IOH = –24 mA 2 2.8
VCC = 4.5 V, IOL = 48 mA 0.3 0.5 V
VCC = 5.5 V, VI = 7 V 0.1 mA
VCC = 5.5 V, VI = 2.7 V 20 µA
VCC = 5.5 V, VI = 0.4 V –0.5 mA
VCC = 5.5 V, VO = 2.25 V –50 –150 mA
VCC = 5.5 V, See Note 2 40 70 mA
grounded, then with CLK and CLR grounded.
MIN MAX UNIT
CLR or PRE low 5
CLK high
CLK low 6
4
ns
switching characteristics over recommended operating free-air temperature range (see Figure 1)
PARAMETER
§
f
max
t
PLH
t
PHL
t
PLH
t
PHL
t
sk(o)
t
sk(p)
t
r
t
§
f
max
f
minimum values are at CL = 0 to 30 pF.
FROM
(INPUT)
or
CLK
CLK Q, Q RL = 500 Ω, CL = 10 pF to 30 pF 1 ns
TO
(OUTPUT)
Q
Q
Q, Q
TEST CONDITIONS MIN MAX UNIT
80 MHz
=
L
=
L
RL = 500 Ω,
,
,
p
=
L
p
= 50
L
CL = 10 pF to 30 pF,
2 9
2 9
3 12
3 12
4.5 ns
3.5 ns
1
ns
1
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
(see Note A)
CLR
or
PRE
t
w
CLK
Q
NOTES: A. CL includes probe and jig capacitance.
B. Input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, tr = 2.5 ns, tf = 2.5 ns.
1.3 V
t
su
1.3 V
Test Point
R
C
L
LOAD CIRCUIT
t
PLH
1.3 V 1.3 V
L
1.3 V
t
PHL
3.5 V
0 V
3.5 V
0.3 V
V
OH
V
OL
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC303
OCTAL DIVIDE-BY-2 CIRCUIT/CLOCK DRIVER
SCAS323A – JULY 1990 – REVISED NOVEMBER 1995
PARAMETER MEASUREMENT INFORMATION
1
CLR, PRE
0
CLK
t
PHL1
Q1
t
PLH1
Q2
Q3
Q4
Q5
Q6
Q
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PHL7
7
t
PHL8
t
PLH7
t
PLH8
t
PHL2
t
PHL3
t
PHL4
t
PHL5
t
PHL6
NOTES: A. t
B. t
C. t
D. t
8
Q
, CLK to Q, is calculated as the greater of:
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
, CLK to Q
sk(o)
, CLK to Q and Q
sk(o)
– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t
is calculated as the greater of | t
sk(p)
, is calculated as the greater of: | t
, is calculated as the greater of:
– t
PLHn
PHLn
Figure 2. Waveforms for Calculation of t
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
( n = 1, 2, 3, 4, 5, 6)
PLHn
( n = 1, 2, 3, 4, 5, 6)
PHLn
– t
PLH7
PLHn
PHLn
| ( n = 1, 2, 3, . . ., 8 ).
| and | t
PLH8
( n = 1, 2, 3, 4, 5, 6), t
( n = 1, 2, 3, 4, 5, 6), t
PHL7
sk(o)
– t
PHL8
and t
PHL7
PLH7
|.
, and t
, and t
sk(p)
PHL8
PLH8
5
PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2005
PACKAGING INFORMATION
Orderable Device Status
(1)
Package
Type
Package
Drawing
Pins Package
Qty
Eco Plan
CDC303D ACTIVE SOIC D 16 Green (RoHS &
no Sb/Br)
CDC303DR ACTIVE SOIC D 16 Green (RoHS &
no Sb/Br)
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in
a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS) or Green (RoHS & no Sb/Br) - please check
http://www.ti.com/productcontent for the latest availability information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements
for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered
at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame
retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material)
(3)
MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder
temperature.
(2)
Lead/Ball Finish MSL Peak Temp
CU NIPD Level-1-260C-UNLIM
CU NIPD Level-1-260C-UNLIM
(3)
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Addendum-Page 1
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