Texas Instruments CDC2586PAHR, CDC2586PAH Datasheet

CDC2586

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

Operates at 3.3-V V

CC

D

Distributes One Clock Input to Twelve
Outputs

D

Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency

D

No External RC Network Required

D

External Feedback (FBIN) Synchronizes the
Outputs to the Clock Input

D

Application for Synchronous DRAM,
High-Speed Microprocessor

D

TTL-Compatible Inputs and Outputs

D

Outputs Have Internal 26-Ω Series
Resistors to Dampen Transmission-Line
Effects

D

State-of-the-Art

EPIC-ΙΙB

 BiCMOS Design

Significantly Reduces Power Dissipation

D

Distributed VCC and Ground Pins Reduce
Switching Noise

D

Packaged in 52-Pin Thin Quad Flat Package

CC

PAH PACKAGE

(TOP VIEW)

15 16

V

CC

4Y3
GND
V

CC

4Y2
GND
V

CC

4Y1
GND
GND
V

CC

3Y3
GND

39
38
37
36
35
34
33
32
31
30
29
28
27

17

1
2
3
4
5
6
7
8
9
10
11
12
13

GND

1Y1

V

CC

GND

1Y2

V

CC

GND

1Y3

V

CC

GND
GND

2Y1

V

CC

18 19 20 21

CLKIN

NCVOE

51 50 49 48 4752 46

GND

SEL1

SEL0

GND

FBIN

AGND

AV

GND

3Y2

V

GND

2Y3

GND

GND

3Y1

44 43 4245

22 23 24 25 26

41 40

14

GND

2Y2

TEST

CLR

CC

CC

V

CC

V

CC

V

CC

NC – No internal connection

A

A

description

The CDC2586 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is
specifically designed for use with popular microprocessors operating at speeds from 50 MHz to 100 MHz or
down to 25 MHz on outputs configured for half-frequency operation. Each output has an internal 26-Ω series
resistor that improves the signal integrity at the load. The CDC2586 operates at nominal 3.3-V V

CC

.

The feedback input (FBIN) synchronizes the output clocks in frequency and phase to CLKIN. One of the twelve
output clocks must be fed back to FBIN for the PLL to maintain synchronization between CLKIN and the outputs.
The output used as feedback is synchronized to the same frequency as CLKIN.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

EPIC-ΙΙΒ is a trademark of Texas Instruments Incorporated.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CDC2586

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

description (continued)

The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. Select inputs
(SEL1, SEL0) configure up to nine Y outputs, in banks of three, to operate at one-half or double the CLKIN
frequency depending on which output is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles
are adjusted to 50% independent of the duty cycle at CLKIN.

Output-enable (OE

) provides output control. When OE is high, the outputs are in the high-impedance state.

When OE

is low, the outputs are active. TEST is used for factory testing of the device and can be used to bypass

the PLL. TEST should be strapped to GND for normal operation.
Unlike many products containing PLLs, the CDC2586 does not require external RC networks. The loop filter

for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2586 requires a stabilization time to achieve phase lock of the

feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of the select inputs, enabling of the PLL via TEST , and upon
enable of all outputs via OE

.

The CDC2586 is characterized for operation from 0°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2586 PLL has a frequency range of 100 MHz to
200 MHz, twice the operating frequency range of the CDC2586 outputs. The output of the VCO is divided by
two and four to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO
frequency. The SEL0 and SEL1 inputs select which of the two signals are buffered to each bank of device
outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency and phase of this output matches that of the CLKIN signal. In the case that a VCO/2 output is wired
to FBIN, the VCO must operate at twice the CLKIN frequency resulting in device outputs that operate at either
the same or one-half the CLKIN frequency. If a VCO/4 output is wired to FBIN, the device outputs operate at
twice or the same as the CLKIN frequency.

CDC2586

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

output configuration A

Output configuration A is valid when any output configured as a 1 frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2 outputs operate at half the CLKIN frequency, while outputs configured as 1 outputs
operate at the same frequency as CLKIN.

Table 1. Output Configuration A

INPUTS

OUTPUTS

SEL1 SEL0

1/2

FREQUENCY

1

FREQUENCY

L L None All
L H 1Yn 2Yn, 3Yn, 4Yn
H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

output configuration B

Output configuration B is valid when any output configured as a 1 frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1 outputs operate at the CLKIN frequency , while outputs configured as 2 outputs operate at
double the frequency of CLKIN.

Table 2. Output Configuration B

INPUTS

OUTPUTS

SEL1 SEL0

1

FREQUENCY

2

FREQUENCY

L L All None
L H 1Yn 2Yn, 3Yn, 4Yn

H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

CDC2586

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS

SCAS337C – FEBRUARY 1993 – REVISED OCTOBER 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

ОООООО

ОООООО

ОООООО

Phase-Lock Loop

One of Four Identical

Outputs – 1Yn

One of Four Identical

Outputs – 2Yn

One of Four Identical

Outputs – 3Yn

One of Four Identical

Outputs – 4Yn

CLR

CLK

TEST

SEL1

SEL0

FBIN

OE

Select

Logic

1Y1–1Y3

2Y1–2Y3

3Y1–3Y3

4Y1–4Y3

÷2

CLR

÷2