TEXAS INSTRUMENTS CDC2582 Technical data

查询CDC2582供应商

D

Low Output Skew for Clock-Distribution
and Clock-Generation Applications

D

Operates at 3.3-V V

D

Distributes Differential LVPECL Clock
Inputs to 12 TTL-Compatible Outputs

D

Two Select Inputs Configure Up to Nine
Outputs to Operate at One-Half or Double
the Input Frequency

D

No External RC Network Required

D

External Feedback Input (FBIN) Is Used to
Synchronize the Outputs With the Clock
Inputs

CC

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

D

Application for Synchronous DRAMs

D

Outputs Have Internal 26-Ω Series
Resistors to Dampen Transmission-Line
Effects

D

D

D

PAH PACKAGE

(TOP VIEW)

State-of-the-Art
Significantly Reduces Power Dissipation

Distributed VCC and Ground Pins Reduce
Switching Noise

Packaged in 52-Pin Quad Flatpack

EPIC-ΙΙB

 BiCMOS Design

CDC2582

GND

1Y1

V

CC

GND

1Y2

V

CC

GND

1Y3

V

CC

GND
GND

2Y1

V

CC

GND

SEL1

51 50 49 48 4752 46

1
2
3
4
5
6
7
8
9
10
11
12
13

15 16

14

2Y2

GND

SEL0

AGND

18 19 20 21

17

CC

V

GND

FBIN

AGND

CC

V

2Y3

CC

V
A

GND

CC

V

CLKIN

CLKINAOE

44 43 4245

22 23 24 25 26

3Y1

GND

V

41 40

CC

GND

TEST

CLR

39
38
37
36
35
34
33
32
31
30
29
28
27

CC

V

3Y2

V

CC

4Y3
GND
V

CC

4Y2
GND
V

CC

4Y1
GND
GND
V

CC

3Y3
GND

description

The CDC2582 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align the frequency and phase of the clock output signals to the differential LVPECL clock (CLKIN,
CLKIN

) input signals. It is specifically designed to operate at speeds from 50 MHz to 100 MHz or down to 25 MHz
on outputs configured as half-frequency outputs. Each output has an internal 26-Ω series resistor that improves
the signal integrity at the load. The CDC2582 operates at 3.3-V VCC.

The feedback input (FBIN) synchronizes the frequency of the output clocks with the input clock (CLKIN, CLKIN)
signals. One of the twelve output clocks must be fed back to FBIN for the PLL to maintain synchronization
between the differential CLKIN and CLKIN

inputs and the outputs. The output used as feedback is synchronized

to the same frequency as the clock (CLKIN and CLKIN) inputs.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1996, Texas Instruments Incorporated

1

CDC2582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

description (continued)

The Y outputs can be configured to switch in phase and at the same frequency as differential clock inputs (CLKIN
and CLKIN). Select (SEL1, SEL0) inputs configure up to nine Y outputs, in banks of three, to operate at one-half
or double the differential clock input frequency, depending upon the feedback configuration (see Tables 1
and 2). All output signal duty cycles are adjusted to 50% independent of the duty cycle at the input clocks.

Output-enable (OE

) is provided for output control. When OE is high, the outputs are in the low state. When OE
is low, the outputs are active. CLR is negative-edge triggered and can be used to reset the outputs operating
at half frequency . TEST is used for factory testing of the device and can be used to bypass the PLL. TEST should
be strapped to GND for normal operation.

Unlike many products containing a PLL, the CDC2582 does not require external RC networks. The loop filter
for the PLL is included on chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2582 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN and CLKIN, as well as following any changes to the PLL
reference or feedback signal. Such changes occur upon change of SEL1 and SEL0, enabling the PLL via TEST ,
and upon enable of all outputs via OE

.

The CDC2582 is characterized for operation from 0°C to 70°C.

detailed description of output configurations

The voltage-controlled oscillator (VCO) used in the CDC2582 has a frequency range of 100 MHz to 200 MHz,
twice the operating frequency range of the CDC2582 outputs. The output of the VCO is divided by 2 and by 4
to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL0
and SEL1 determine which of the two signals are buffered to each bank of device outputs.

One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of this output matches that of the CLKIN/CLKIN signals. In the case that a VCO/2 output is wired to
FBIN, the VCO must operate at twice the CLKIN/CLKIN frequency , resulting in device outputs that operate at
the same or one-half the CLKIN/CLKIN frequency . If a VCO/4 output is wired to FBIN, the device outputs operate
at the same or twice the CLKIN/CLKIN

frequency.

output configuration A

Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
FBIN. The frequency range for the differential clock input is 50 MHz to 100 MHz when using output configuration
A. Outputs configured as 1/2× outputs operate at half the input clock frequency , while outputs configured as 1×
outputs operate at the same frequency as the differential clock input.

Table 1. Output Configuration A

INPUTS

SEL1 SEL0

L L None All

L H 1Yn 2Yn, 3Yn, 4Yn
H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

FREQUENCY1×FREQUENCY

OUTPUTS

1/2×

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

output configuration B

Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The frequency range for the differential clock inputs is 25 MHz to 50 MHz when using output configuration
B. Outputs configured as 1× outputs operate at the input clock frequency , while outputs configured as 2× outputs
operate at double the frequency of the differential clock inputs.

Table 2. Output Configuration B

CDC2582

INPUTS

SEL1 SEL0

L L All None
L H 1Yn 2Yn, 3Yn, 4Yn

H L 1Yn, 2Yn 3Yn, 4Yn
H H 1Yn, 2Yn, 3Yn 4Yn

NOTE: n = 1, 2, 3

FREQUENCY2×FREQUENCY

OUTPUTS

1×

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

3

CDC2582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

functional block diagram

OE

CLR

FBIN

CLKIN
CLKIN

TEST

SEL0

SEL1

Phase-Lock Loop

Select

Logic

B

2

One of Three Identical

Outputs – 1Yn

One of Three Identical

Outputs – 2Yn

B

CLR

2

1Y1–1Y3

2Y1–2Y3

One of Three Identical

Outputs – 3Yn

One of Three Identical

Outputs – 4Yn

3Y1–3Y3

4Y1–4Y3

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

I/O

DESCRIPTION

TERMINAL

NAME NO.

CLKIN
CLKIN

CLR 40 I

FBIN 48 I

OE 42 I

SEL1, SEL0 51, 50 I

TEST 41 I

1Y1–1Y3
2Y1–2Y3
3Y1–3Y3

4Y1–4Y3 32, 35, 38 O

44, 45 I

2, 5, 8
12, 15, 18
22, 25, 28

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

Terminal Functions

Clock input. CLKIN and CLKIN are the differential clock signals to be distributed by the CDC2582
clock-driver circuit. These inputs are used to provide the reference signal to the integrated PLL that
generates the clock-output signals. CLKIN and CLKIN
PLL to obtain phase lock. Once the circuit is powered up and valid CLKIN and CLKIN
a stabilization time is required for the PLL to phase lock the feedback signal to its reference signal.

Clear. CLR is used to reset the VCO/4 reference frequency . CLR is negative-edge triggered and should be
strapped to VCC or GND for normal operation.

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hardwired to one of
the twelve clock outputs to provide frequency and phase lock. The internal PLL adjusts the output clocks
to obtain zero-phase delay between the FBIN and the differential clock input (CLKIN and CLKIN

Output enable. OE is the output enable for all outputs. When OE is low, all outputs are enabled. When OE
is high, all outputs are in the high-impedance state. Since the feedback signal for the PLL is taken directly
from an output terminal, placing the outputs in the high-impedance state interrupts the feedback loop;
therefore, when a high-to-low transition occurs at OE
required before the PLL obtains phase lock.

Output configuration select. SEL0 and SEL1 select the output configuration for each output bank
(e.g., 1×, 1/2×, or 2×) (see Tables 1 and 2).

TEST is used to bypass the PLL circuitry for factory testing of the device. When TEST is low, all outputs
operate using the PLL circuitry. When TEST is high, the outputs are placed in a test mode that bypasses
the PLL circuitry. TEST should be strapped to GND for normal operation.

These outputs are configured by SEL1 and SEL0 to transmit one-half or one-fourth the frequency of the
VCO. The relationship between the input clock frequency and the output frequency is dependent on SEL1

O

and SEL0 and the frequency of the output being fed back to FBIN. The duty cycle of the Y outputs is
nominally 50% independent of the duty cycle of the input clock signals. Each output has an internal series
resistor to dampen transmission-line effects and improve the signal integrity at the load.

These outputs transmit one-half the frequency of the VCO. The relationship between the input clock
frequency and the output frequency is dependent on the frequency of the output being fed back to FBIN.
The duty cycle of the Y outputs is nominally 50% independent of the duty cycle of CLKIN. Each output has
an internal series resistor to dampen transmission-line effects and improve the signal integrity at the load.

must have a fixed frequency and fixed phase for the

signals are applied,

, enabling the output buffers, a stabilization time is

CDC2582

).

absolute maximum ratings over operating free-air temperature range (unless otherwise noted)

Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Input voltage range, VI (see Note 1) –0.5 V to 7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Voltage range applied to any output in the high state or power-off state, V
Current into any output in the low state, I
Input clamp current, I
Output clamp current, I

(V

< 0) –20 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

IK

I

(V

OK

< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

24 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

O

Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 1.2 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

Storage temperature range, T

†

Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.

2. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the

Book

, literature number SCBD002.

–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

stg

Package Thermal Considerations

application note in the

(see Note 1) –0.5 V to 5.5 V. . .

O

ABT Advanced BiCMOS T echnology Data

†

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

5

CDC2582

VIHHigh-level input voltage

V

VILLow-level input voltage

V

PARAMETER

TEST CONDITIONS

UNIT

V

V

V

V

V

V

I

A

I

CC

,

O

,

mA

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

recommended operating conditions (see Note 3)

MIN MAX UNIT

V

CC

V

I

I

OH

I

OL

T

A

NOTE 3: Unused inputs must be held high or low to prevent them from floating.

electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)

†

For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.

Supply voltage 3 3.6 V

p

p

Input voltage 0 5.5 V
High-level output current –12 mA
Low-level output current 12 mA
Operating free-air temperature 0 70 °C

V

C
C

IK

OH

OL

I

CC

i
o

VCC = 3 V, II = –18 mA –1.2 V
VCC = MIN to MAX†, IOH = –100 µA VCC–0.2
VCC = 3 V, IOH = – 12 mA 2

= 3

CC

VCC = 0 or MAX†, VI = 3.6 V ±10
VCC = 3.6 V, VI = VCC or GND ±1

V

= 3.6 V, I

VI = VCC or GND
VI = 3 V or 0 4 pF

VO = 3 V or 0 8 pF

CLKIN, CLKIN VCC–1.025
Other inputs 2
CLKIN, CLKIN VCC–1.62
Other inputs 0.8

TA = 25°C
MIN MAX

IOL = 100 µA 0.2
IOL = 12 mA 0.8

= 0,

Outputs high 5
Outputs low 5

µ

6

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

f

Clock frequenc

MH

†

CDC2582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

timing requirements over recommended ranges of supply voltage and operating free-air
temperature

MIN MAX UNIT

clock

Input clock duty cycle 40% 60%

Stabilization time

†

Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLKIN. Until phase lock is obtained, the specifications for propagation delay
and skew parameters given in the switching characteristics table are not applicable.

y

switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C

PARAMETER

Duty cycle Y 45% 55%
f

max

Jitter
t

phase error

t

sk(o)

t

sk(pr)

t

r

t

‡

The propagation delay, t
are only valid for equal loading of all outputs.

NOTE 4: The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.

f

= 15 pF (see Note 4 and Figures 1, 2, and 3)

L

(pk-pk)

‡

‡

‡

phase error

, is dependent on the feedback path from any output to FBIN. The t

VCO is operating at four times the CLKIN/CLKIN frequency 25 50
VCO is operating at double the CLKIN/CLKIN

After SEL1, SEL0 50
After OE↓ 50
After power up 50

FROM

(INPUT)

CLKIN↑ Y↑ 200 ps
CLKIN↑ Y –500 500 ps

(OUTPUT)

frequency 50 100

TO

Y 0.5 ns
Y 1 ns

phase error

MIN MAX UNIT

100 MHz

, t

, and t

sk(o)

1.4 ns

1.4 ns
specifications

sk(pr)

µs

z

PARAMETER MEASUREMENT INFORMATION

From Output

Under Test

CL = 15 pf

(see Note A)

LOAD CIRCUIT FOR OUTPUTS

NOTES: A. CL includes probe and jig capacitance.

B. The outputs are measured one at a time with one transition per measurement.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 10 MHz, ZO = 50 Ω, tr ≤ 2.5 ns, tf≤ 2.5 ns.

Figure 1. Load Circuit and Voltage Waveforms

CLKIN

CLKIN

t

phase error

Output

500 Ω

PROPAGATION DELAY TIMES

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

2 V

2 V

0.8 V

t

r

VOLTAGE WAVEFORMS

1.5 V

t

f

2 V

2 V

0.8 V

2.4 V

1.6 V

V

OH

V

OL

7

CDC2582

3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

CLKIN

CLKIN

t

phase error 1

Outputs

Operating

at 1/2 CLKIN

Frequency

t

phase error 2

t

phase error 3

Outputs

Operating

at CLKIN

Frequency

NOTES: A. Output skew, t

– The difference between the fastest and slowest of t
– The difference between the fastest and slowest of t

B. Process skew, t

– The difference between the maximum and minimum t

operating conditions

– The difference between the maximum and minimum t

operating conditions

t

phase error 4

t

phase error 5

t

phase error 6

, is calculated as the greater of:

sk(o)

, is calculated as the greater of:

sk(pr)

Figure 2. Skew Waveforms and Calculations

phase error n
phase error n

phase error n

phase error n

t

phase error 7

t

phase error 8

t

phase error 9

(n = 1, 2,...6)
(n = 7, 8, 9)

(n = 1, 2, . .. 6) across multiple devices under identical

(n = 7, 8, 9) across multiple devices under identical

8

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Operating

at CLKIN

Frequency

Outputs

CLKIN

CLKIN

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

WITH DIFFERENTIAL LVPECL CLOCK INPUTS

SCAS379B – FEBRUARY 1993 – REVISED FEBRUARY 1996

PARAMETER MEASUREMENT INFORMATION

t

phase error 10

t

phase error 11

t

phase error 12

CDC2582

Outputs

Operating

at 2X CLKIN

Frequency

NOTES: A. Output skew, t

– The difference between the fastest and slowest of t

B. Process skew, t

– The difference between the maximum and minimum t

operating conditions

t

phase error 13

t

phase error 14

t

phase error 15

, is calculated as the greater of:

sk(o)

, is calculated as the greater of:

sk(pr)

phase error n

phase error n

Figure 3. Waveforms for Calculation of t

(n = 10, 11,...15)

(n = 10, 11,. . . 15) across multiple devices under identical

and t

sk(o)

sk(pr)

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

9

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