Texas Instruments CDC2536DLR, CDC2536DL, CDC2536DBR Datasheet
CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS377D – APRIL 1994 – REVISED OCTOBER 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Low Output Skew for Clock-Distribution
and Clock-Generation Applications
D
Operates at 3.3-V V
CC
D
Distributes One Clock Input to Six Outputs
D
One Select Input Configures Three Outputs
to Operate at One-Half or Double the Input
Frequency
D
No External RC Network Required
D
On-Chip Series Damping Resistors
D
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D
Application for Synchronous DRAM,
High-Speed Microprocessor
D
TTL-Compatible Inputs and Outputs
D
Outputs Drive 50-Ω Parallel-Terminated
Transmission Lines
D
State-of-the-Art
EPIC-ΙΙB
BiCMOS Design
Significantly Reduces Power Dissipation
D
Distributed VCC and Ground Pins Reduce
Switching Noise
D
Packaged in Plastic 28-Pin Shrink
Small-Outline Package
description
The CDC2536 is a high-performance, low-skew, low-jitter clock driver. It uses a phase-lock loop (PLL) to
precisely align, in both frequency and phase, the clock output signals to the clock input (CLKIN) signal. It is
specifically designed for use with synchronous DRAMs and popular microprocessors operating at speeds from
50 MHz to 100 MHz or down to 25 MHz on outputs configured as half-frequency outputs. The CDC2536
operates at 3.3-V V
CC
and is designed to drive a 50-W transmission line. The CDC2536 also provides on-chip
series-damping resistors, eliminating the need for external termination components.
The feedback (FBIN) input is used to synchronize the output clocks in frequency and phase to the input clock
(CLKIN). One of the six output clocks must be fed back to FBIN for the PLL to maintain synchronization between
CLKIN and the outputs. The output used as the feedback pin is synchronized to the same frequency as CLKIN.
The Y outputs can be configured to switch in phase and at the same frequency as CLKIN. The select (SEL)
input configures three Y outputs to operate at one-half or double the CLKIN frequency , depending on which pin
is fed back to FBIN (see Tables 1 and 2). All output signal duty cycles are adjusted to 50% independent of the
duty cycle at the input clock.
Output-enable (OE
) is provided for output control. When OE is high, the outputs are in the high-impedance state.
When OE
is low, the outputs are active. TEST is used for factory testing of the device and can be use to bypass
the PLL. TEST should be strapped to GND for normal operation.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
EPIC-ΙΙB is a trademark of Texas Instruments Incorporated.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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28
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AV
CC
AGND
CLKIN
SEL
OE
GND
1Y1
V
CC
GND
1Y2
V
CC
GND
1Y3
V
CC
AV
CC
AGND
FBIN
TEST
CLR
V
CC
2Y1
GND
V
CC
2Y2
GND
V
CC
2Y3
GND
DB PACKAGE
(TOP VIEW)
CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS377D – APRIL 1994 – REVISED OCTOBER 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
description (continued)
Unlike many products containing PLLs, the CDC2536 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2536 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLKIN, as well as following any changes to the PLL reference or
feedback signals. Such changes occur upon change of SEL, enabling the PLL via TEST, and upon enable of
all outputs via OE
.
The CDC2536 is characterized for operation from 0°C to 70°C.
detailed description of output configurations
The voltage-controlled oscillator (VCO) used in the CDC2536 has a frequency range of 100 MHz to 200 MHz,
twice the operating frequency of the CDC2536 outputs. The output of the VCO is divided by two and by four
to provide reference frequencies with a 50% duty cycle of one-half and one-fourth the VCO frequency. SEL
determines which of the two signals is buffered to each bank of device outputs.
One device output must be externally wired to FBIN to complete the PLL. The VCO operates such that the
frequency of the output matches that of CLKIN. In the case that a VCO/2 output is wired to FBIN, the VCO must
operate at twice the CLKIN frequency resulting in device outputs that operate at either the same or one-half the
CLKIN frequency . If a VCO/4 output is wired to FBIN, the device outputs operate at the same or twice the CLKIN
frequency .
output configuration A
Output configuration A is valid when any output configured as a 1× frequency output in Table 1 is fed back to
FBIN. The input frequency range for CLKIN is 50 MHz to 100 MHz when using output configuration A. Outputs
configured as 1/2× outputs operate at half the CLKIN frequency , while outputs configured as 1× outputs operate
at the same frequency as CLKIN.
Table 1. Output Configuration A
INPUT
OUTPUTS
SEL
1/2×
FREQUENCY1×FREQUENCY
L None All
H 1Yn 2Yn
NOTE: n = 1, 2, 3
output configuration B
Output configuration B is valid when any output configured as a 1× frequency output in Table 2 is fed back to
FBIN. The input frequency range for CLKIN is 25 MHz to 50 MHz when using output configuration B. Outputs
configured as 1× outputs operate at the CLKIN frequency, while outputs configured as 2× outputs operate at
double the frequency of CLKIN.
Table 2. Output Configuration B
INPUT
OUTPUTS
SEL
1×
FREQUENCY2×FREQUENCY
H 1Yn 2Yn
L All None
NOTE: n = 1, 2, 3
CDC2536
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
WITH 3-STATE OUTPUTS
SCAS377D – APRIL 1994 – REVISED OCTOBER 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
2Y3
2Y2
2Y1
1Y3
1Y2
1Y1
Phase-Lock Loop
CLR
CLKIN
TEST
SEL
FBIN
OE
B
2
B
2
5
24
26
3
25
4
7
10
13
22
19
16
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