Texas Instruments CDC2516DGGR Datasheet

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

1

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D

Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications

D

Distributes One Clock Input to Four Banks
of Four Outputs

D

Separate Output Enable for Each Output
Bank

D

External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input

D

On-Chip Series-Damping Resistors

D

No External RC Network Required

D

Operates at 3.3-V V

CC

D

Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package

description

The CDC2516 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency
and phase, the feedback output (FBOUT) to the
clock (CLK) input signal. It is specifically designed
for use with synchronous DRAMs. The CDC2516
operates at 3.3-V V

CC

and provides integrated
series-damping resistors that make it ideal for
driving point-to-point loads.

Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.

Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.

Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV

CC

to ground.

The CDC2516 is characterized for operation from 0°C to 70°C.

Copyright  1998, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

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V

CC

1Y0

1Y1
GND
GND

1Y2

1Y3

V

CC

1G

GND

AV

CC

CLK
AGND
AGND

GND

2G

V

CC

2Y0

2Y1
GND
GND

2Y2

2Y3

V

CC

V

CC

4Y0
4Y1
GND
GND
4Y2
4Y3
V

CC

4G
GND
AV

CC

FBIN
AGND
FBOUT
GND
3G
V

CC

3Y0
3Y1
GND
GND
3Y2
3Y3
V

CC

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47
46
45
44
43
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DGG PACKAGE

(TOP VIEW)

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

FUNCTION TABLE

INPUTS

OUTPUTS

1G 2G 3G 4G CLK

1Y

(0:3)2Y(0:3)3Y(0:3)4Y(0:3)

FBOUT

X X X X L L L L L L
L LLLHLLLL H
L LLHHLLLHH
L LHLHLLHL H
L LHHHLLHHH
L HLLHLHLL H
L HLHHLHLHH
L HHLHLHHL H
L HHHHLHHH H
H LLLHHLLLH
H LLHHHLLH H
H LHLHHLHL H
H LHHHHLHH H
H HLLHHHLL H
H HLHHHHLH H
H HHLHHHHL H
H H H H H H H H H H

AVAILABLE OPTIONS

PACKAGE

T

A

SMALL OUTLINE

(DGG)

0°C to 70°C CDC2516DGGR

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

3

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

functional block diagram

3Y2

3Y1

3Y0

PLL

FBIN

AV

CC

4G

CLK

3G

4Y2

4Y1

4Y0

4Y3

FBOUT

3Y3

33

40

12

37

11

31

30

27

26

47

46

43

42

35

2Y2

2Y1

2Y0

2G

2Y3

16

18

19

22

23

1Y2

1Y1

1Y0

1G

1Y3

9

2

3

6

7

CDC2516

3.3-V PHASE-LOCK LOOP CLOCK DRIVER

SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Terminal Functions

TERMINAL

NAME NO.

TYPE

DESCRIPTION

CLK 12 I

Clock input. CLK provides the clock signal to be distributed by the CDC2516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.

FBIN 37 I

Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.

1G 9 I

Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.

2G 16 I

Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.

3G 33 I

Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.

4G 40 I

Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.

FBOUT 35 O

Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.

1Y(0:3) 2, 3, 6, 7 O

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output
has an integrated 25-Ω series-damping resistor.

2Y(0:3) 18, 19, 22, 26 O

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output
has an integrated 25-Ω series-damping resistor.

3Y(0:3) 31, 30, 27, 26 O

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input. Each output
has an integrated 25-Ω series-damping resistor.

4Y(0:3) 47, 46, 43, 42 O

Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input. Each output
has an integrated 25-Ω series-damping resistor.

AV

CC

11, 38 Power

Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V

CC

can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.

AGND 13, 14, 36 Ground Analog ground. AGND provides the ground reference for the analog circuitry.

V

CC

1, 8, 17, 24,

25, 32, 41, 48

Power Power supply

GND

4, 5, 10, 15,

20, 21, 28, 29,

34, 39, 44, 45

Ground Ground