CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to Four Banks
of Four Outputs
D
Separate Output Enable for Each Output
Bank
D
External Feedback Pin (FBIN) Is Used to
Synchronize the Outputs to the Clock Input
D
On-Chip Series-Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V V
CC
D
Packaged in Plastic 48-Pin Thin Shrink
Small-Outline Package
description
The CDC2516 is a high-performance, low-skew,
low-jitter, phase-lock loop (PLL) clock driver. It
uses a PLL to precisely align, in both frequency
and phase, the feedback output (FBOUT) to the
clock (CLK) input signal. It is specifically designed
for use with synchronous DRAMs. The CDC2516
operates at 3.3-V V
CC
and provides integrated
series-damping resistors that make it ideal for
driving point-to-point loads.
Four banks of four outputs provide 16 low-skew,
low-jitter copies of the input clock. Output signal
duty cycles are adjusted to 50 percent,
independent of the duty cycle at the input clock.
Each bank of outputs can be enabled or disabled
separately via the 1G, 2G, 3G, and 4G control
inputs. When the G inputs are high, the outputs
switch in phase and frequency with CLK; when the
G inputs are low, the outputs are disabled to the
logic-low state.
Unlike many products containing PLLs, the CDC2516 does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry, the CDC2516 requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required following power up and application
of a fixed-frequency, fixed-phase signal at CLK, as well as following any changes to the PLL reference or
feedback signals. The PLL may be bypassed for test purposes by strapping AV
CC
to ground.
The CDC2516 is characterized for operation from 0°C to 70°C.
Copyright 1998, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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5
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7
8
9
10
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12
13
14
15
16
17
18
19
20
21
22
23
24
V
CC
1Y0
1Y1
GND
GND
1Y2
1Y3
V
CC
1G
GND
AV
CC
CLK
AGND
AGND
GND
2G
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
V
CC
4Y0
4Y1
GND
GND
4Y2
4Y3
V
CC
4G
GND
AV
CC
FBIN
AGND
FBOUT
GND
3G
V
CC
3Y0
3Y1
GND
GND
3Y2
3Y3
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
DGG PACKAGE
(TOP VIEW)
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
FUNCTION TABLE
INPUTS
OUTPUTS
1G 2G 3G 4G CLK
1Y
(0:3)2Y(0:3)3Y(0:3)4Y(0:3)
FBOUT
X X X X L L L L L L
L LLLHLLLL H
L LLHHLLLHH
L LHLHLLHL H
L LHHHLLHHH
L HLLHLHLL H
L HLHHLHLHH
L HHLHLHHL H
L HHHHLHHH H
H LLLHHLLLH
H LLHHHLLH H
H LHLHHLHL H
H LHHHHLHH H
H HLLHHHLL H
H HLHHHHLH H
H HHLHHHHL H
H H H H H H H H H H
AVAILABLE OPTIONS
PACKAGE
T
A
SMALL OUTLINE
(DGG)
0°C to 70°C CDC2516DGGR
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
functional block diagram
3Y2
3Y1
3Y0
PLL
FBIN
AV
CC
4G
CLK
3G
4Y2
4Y1
4Y0
4Y3
FBOUT
3Y3
33
40
12
37
11
31
30
27
26
47
46
43
42
35
2Y2
2Y1
2Y0
2G
2Y3
16
18
19
22
23
1Y2
1Y1
1Y0
1G
1Y3
9
2
3
6
7
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME NO.
TYPE
DESCRIPTION
CLK 12 I
Clock input. CLK provides the clock signal to be distributed by the CDC2516 clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
FBIN 37 I
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
1G 9 I
Output bank enable. 1G is the output enable for outputs 1Y(0:3). When 1G is low, outputs 1Y(0:3) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:3) are enabled and switch at the same
frequency as CLK.
2G 16 I
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic-low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
3G 33 I
Output bank enable. 3G is the output enable for outputs 3Y(0:3). When 3G is low, outputs 3Y(0:3) are
disabled to a logic-low state. When 3G is high, all outputs 3Y(0:3) are enabled and switch at the same
frequency as CLK.
4G 40 I
Output bank enable. 4G is the output enable for outputs 4Y(0:3). When 4G is low, outputs 4Y(0:3) are
disabled to a logic-low state. When 4G is high, all outputs 4Y(0:3) are enabled and switch at the same
frequency as CLK.
FBOUT 35 O
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
1Y(0:3) 2, 3, 6, 7 O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 1Y(0:3) are enabled via 1G.
These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each output
has an integrated 25-Ω series-damping resistor.
2Y(0:3) 18, 19, 22, 26 O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 2Y(0:3) are enabled via 2G.
These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each output
has an integrated 25-Ω series-damping resistor.
3Y(0:3) 31, 30, 27, 26 O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 3Y(0:3) are enabled via 3G.
These outputs can be disabled to a logic-low state by deasserting the 3G control input. Each output
has an integrated 25-Ω series-damping resistor.
4Y(0:3) 47, 46, 43, 42 O
Clock outputs. These outputs provide low-skew copies of CLK. Outputs 4Y(0:3) are enabled via 4G.
These outputs can be disabled to a logic-low state by deasserting the 4G control input. Each output
has an integrated 25-Ω series-damping resistor.
AV
CC
11, 38 Power
Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
CC
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, the PLL is
bypassed and CLK is buffered directly to the device outputs.
AGND 13, 14, 36 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
1, 8, 17, 24,
25, 32, 41, 48
Power Power supply
GND
4, 5, 10, 15,
20, 21, 28, 29,
34, 39, 44, 45
Ground Ground
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
†
Supply voltage range, V
CC
–0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high
or low state, VO (see Notes 1 and 2) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
(V
I
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
OK
(V
O
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous output current, I
O
(V
O
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 3) 0.85 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
stg
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. This value is limited to 4.6 V maximum.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
Book
, literature number SCBD002.
recommended operating conditions (see Note 4)
MIN MAX UNIT
V
CC
Supply voltage 3 3.6 V
V
IH
High-level input voltage 2 V
V
IL
Low-level input voltage 0.8 V
V
I
Input voltage 0 V
CC
V
I
OH
High-level output current –12 mA
I
OL
Low-level output current 12 mA
T
A
Operating free-air temperature 0 70 °C
NOTE 4: Unused inputs must be held high or low to prevent them from floating.
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS V
CC
MIN TYP‡MAX UNIT
V
IK
II = –18 mA 3 V –1.2 V
IOH = –100 µA MIN to MAX VCC–0.2
V
OH
IOH = –12 mA 3 V 2.4
V
IOH = –6 mA 3 V 2.1
IOL = 100 µA MIN to MAX 0.2
V
OL
IOL = 12 mA 3 V 0.8
V
IOL = 6 mA 3 V 0.55
I
I
VI = VCC or GND 3.6 V ±5 µA
I
CC
§
VI = VCC or GND IO = 0, Outputs: low or high 3.6 V 20 µA
∆I
CC
One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA
C
i
VI = VCC or GND 3.3 V 4 pF
C
o
VO = VCC or GND 3.3 V 6 pF
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§
For ICC of AVCC, see Figure 5. For dynamic digital ICC, see Figure 6.
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
MIN MAX UNIT
f
clock
Clock frequency 25 125 MHz
Input clock duty cycle 40% 60%
Stabilization time
†
1 ms
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
L
= 30 pF (see Note 5 and Figures 1 and 2)
‡
PARAMETER
FROM
TO
VCC = 3.3 V
± 0.165 V
VCC = 3.3 V
± 0.3 V
UNIT
(INPUT)
(OUTPUT)
MIN TYP MAX MIN TYP MAX
t
phase error
reference
(see Figure 3)
66 MHz < CLKIN↑ < 100 MHz FBIN↑ –0.7...0.18 ns
t
phase error
, – jitter,
(see Note 6)
CLKIN↑ = 100 MHz FBIN↑ –360 50 –170 ps
t
sk(o)
§
Any Y or FBOUT Any Y or FBOUT 200 ps
Jitter
(pk-pk)
F(clkin > 66 MHz) Any Y or FBOUT –100 100 ps
F(clkin ≤ 66 MHz) Any Y or FBOUT 45% 55%
Duty cycle
F(clkin > 66 MHz) Any Y or FBOUT 43% 55%
t
r
Any Y or FBOUT 1.3 1.9 0.7 2.1 ns
t
f
Any Y or FBOUT 1.7 2.5 1.2 2.5 ns
‡
These parameters are not production tested.
§
The t
sk(o)
specification is only valid for equal loading of all outputs.
NOTES: 5. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
6. Phase error does not include jitter. The total phase error is –460 ps to 150 ps for the 5% VCC range.
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
7
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
LOAD CIRCUIT
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
t
pd
50% V
CC
3 V
0 V
V
OH
V
OL
Input
0.4 V
2 V
t
r
t
f
0.4 V
2 V
Output
500
W
50% V
CC
30 pF
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
50% V
CC
Figure 1. Load Circuit and Voltage Waveforms
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
8
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
sk(o)
t
sk(o)
t
phase error
CLKIN
FBIN
Any Y
Any Y
Any Y
FBOUT
Figure 2. Phase Error and Skew Calculations
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPICAL CHARACTERISTICS
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
–400
–600
–800
–1000
55 95
f
clk
– Clock Frequency – MHz
–300
–500
–700
–900
75 115 135
VDD = 3.3 V
TA = 25°C
–200
0
35
Phase Error – ps
–100
Figure 4
VDD = 3.3 V
CL = 30 pF
OUTPUT DUTY CYCLE
vs
CLOCK FREQUENCY
57%
53%
51%
47%
43%
55%
49%
45%
Output Duty Cycle
50 70 110
f
clk
– Clock Frequency – MHz
90 13030
Figure 5
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
25
6
4
2
0
35 45 55 85 95
f
clk
– Clock Frequency – MHz
75
7
Analog Supply Current – mA
5
3
1
65 105 115 125
8
9
VDD = 3.3 V
TA = 25°C
Figure 6
DYNAMIC SUPPLY CURRENT
vs
CLOCK FREQUENCY
300
200
100
0
f
clk
– Clock Frequency – MHz
350
Dynamic Supply Current – mA
250
150
50
400
450
500
0 20 40 60 120 14010080
VCC = 3.6 V
Bias = 0/3 V
CL = 30 pF to GND
TA = 25°C
CDC2516
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS579A – OCTOBER 1996 – REVISED JANUARY 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
MECHANICAL INFORMATION
DGG (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
4040078/D 08/96
48 PIN SHOWN
56
14,10
13,90
0,25
48
DIM
A MAX
A MIN
PINS **
0,15 NOM
Gage Plane
6,00
6,20
8,30
7,90
12,40
12,60
0,75
0,50
Seating Plane
25
0,27
0,17
24
A
48
1
0,05 MIN
1,20 MAX
64
17,10
16,90
M
0,08
0,10
0,50
0°–8°
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Falls within JEDEC MO-153
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pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. T esting and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
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BE FULLY AT THE CUSTOMER’S RISK.
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TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
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Copyright 1998, Texas Instruments Incorporated
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