Texas Instruments CDC2510BPWR Datasheet
CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
D
Designed to Meet PC SDRAM Registered
DIMM Specification
D
Spread Spectrum Clock Compatible
D
Operating Frequency 25 MHz to 125 MHz
D
tPhase Error Minus Jitter at 66MHz to
100MHz is ±150ps
D
Jitter (pk – pk) at 66 MHz to 100 MHz is
±80ps
D
Jitter (cyc – cyc) at 66 MHz to 100 MHz is
|100 ps|
D
Available in Plastic 24-Pin TSSOP
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Ten Outputs
D
Separate Output Enable for Each Output
Bank
D
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
FBOUT
PW PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
G
11
12
24
23
22
21
20
19
18
17
16
15
14
13
CLK
AV
CC
V
CC
1Y9
1Y8
GND
GND
1Y7
1Y6
1Y5
V
CC
FBIN
description
The CDC2510B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2510B operates at 3.3-V VCC. It also
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of ten outputs provides ten low-skew, low-jitter copies of CLK. Output signal duty cycles are adjusted
to 50 percent, independent of the duty cycle at CLK. All outputs can be enabled or disabled via a single output
enable input. When the G input is high, the outputs switch in phase and frequency with CLK; when the G input
is low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2510B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry , the CDC2510B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AV
The CDC2510B is characterized for operation from 0°C to 70°C.
For application information refer to application reports
CDC509/516/2509/2510/2516
Spectrum Clocking (SSC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
(literature number SLMA003) and
(literature number SCAA039).
High Speed Distribution Design Techniques for
to ground.
CC
Using CDC2509A/2510A PLL with Spread
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
CDC2510B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS612 – SEPTEMBER 1998
FUNCTION TABLE
INPUTS
G CLK
X L L L
L HLH
H H H H
functional block diagram
11
G
OUTPUTS
1Y
(0:9)
FBOUT
3
1Y0
4
1Y1
5
1Y2
CLK
FBIN
AV
CC
24
13
23
PLL
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C CDC2510BPWR
SMALL OUTLINE
(PW)
15
16
17
20
21
12
8
9
1Y3
1Y4
1Y5
1Y6
1Y7
1Y8
1Y9
FBOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPE
DESCRIPTION
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Terminal Functions
TERMINAL
NAME NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2510B clock driver. CLK is
used to provide the reference signal to the integrated PLL that generates the clock output signals. CLK
CLK 24 I
FBIN 13 I
G 11 I
FBOUT 12 O
3, 4, 5, 8, 9
CC
15, 16, 17, 20,
21
23 Power
2, 10, 14, 22 Power Power supply
1Y (0:9)
AV
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND 6, 7, 18, 19 Ground Ground
must have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is
powered up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock
the feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is
nominally zero phase error between CLK and FBIN.
Output bank enable. G is the output enable for outputs 1Y(0:9). When G is low, outputs 1Y(0:9) are
disabled to a logic-low state. When G is high, all outputs 1Y(0:9) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as
CLK. When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has
an integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:9) is enabled via
the G input. These outputs can be disabled to a logic-low state by deasserting the G control input.
O
Each output has an integrated 25-Ω series-damping resistor.
Analog power supply . A VCC provides the power reference for the analog circuitry. In addition, A V
can be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed
and CLK is buffered directly to the device outputs.
CDC2510B
SCAS612 – SEPTEMBER 1998
CC
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
Loading...