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CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
D
Designed to Meet PC SDRAM Registered
DIMM Specification
D
Spread Spectrum Clock Compatible
D
Operating Frequency 25 MHz to 125 MHz
D
tPhase Error Minus Jitter at 66MHz to
100 MHz is ±150 ps
D
Jitter (pk – pk) at 66 MHz to 100 MHz is
±80 ps
D
Jitter (cyc – cyc) at 66 MHz to 100 MHz is
|100 ps|
D
Available in Plastic 24-Pin TSSOP
D
Phase-Lock Loop Clock Distribution for
Synchronous DRAM Applications
D
Distributes One Clock Input to One Bank of
Five and One Bank of Four Outputs
D
Separate Output Enable for Each Output
Bank
D
External Feedback (FBIN) Terminal Is Used
to Synchronize the Outputs to the Clock
Input
D
On-Chip Series Damping Resistors
D
No External RC Network Required
D
Operates at 3.3-V
AGND
V
CC
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
CC
1G
FBOUT
PW PACKAGE
(TOP VIEW)
1
24
2
23
3
22
4
21
5
20
6
19
7
18
8
17
9
16
10
15
11
14
12
13
CLK
AV
CC
V
CC
2Y0
2Y1
GND
GND
2Y2
2Y3
V
CC
2G
FBIN
description
The CDC2509B is a high-performance, low-skew, low-jitter, phase-lock loop (PLL) clock driver. It uses a PLL
to precisely align, in both frequency and phase, the feedback (FBOUT) output to the clock (CLK) input signal.
It is specifically designed for use with synchronous DRAMs. The CDC2509B operates at 3.3-V V
provides integrated series-damping resistors that make it ideal for driving point-to-point loads.
One bank of five outputs and one bank of four outputs provide nine low-skew , low-jitter copies of CLK. Output
signal duty cycles are adjusted to 50%, independent of the duty cycle at CLK. Each bank of outputs is enabled
or disabled separately via the control (1G and 2G) inputs. When the G inputs are high, the outputs switch in
phase and frequency with CLK; when the G inputs are low, the outputs are disabled to the logic-low state.
Unlike many products containing PLLs, the CDC2509B does not require external RC networks. The loop filter
for the PLL is included on-chip, minimizing component count, board space, and cost.
Because it is based on PLL circuitry , the CDC2509B requires a stabilization time to achieve phase lock of the
feedback signal to the reference signal. This stabilization time is required, following power up and application
of a fixed-frequency, fixed-phase signal at CLK, and following any changes to the PLL reference or feedback
signals. The PLL can be bypassed for test purposes by strapping AVCC to ground.
The CDC2509B is characterized for operation from 0°C to 70°C.
For application information refer to application reports
CDC509/516/2509/2510/2516
Spectrum Clocking (SSC)
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
(literature number SLMA003) and
(literature number SCAA039).
High Speed Distribution Design Techniques for
Using CDC2509A/2510A PLL with Spread
CC
. It also
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1998, Texas Instruments Incorporated
1
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
FUNCTION TABLE
INPUTS
1G 2G CLK
X X L L L L
L LHLLH
L HHLHH
H LHHLH
H H H H H H
functional block diagram
11
1G
OUTPUTS
1Y
(0:4)2Y(0:3)
FBOUT
3
1Y0
4
1Y1
CLK
FBIN
AV
2G
CC
14
24
13
23
PLL
AVAILABLE OPTIONS
PACKAGE
T
A
0°C to 70°C CDC2509BPWR
SMALL OUTLINE
(PW)
21
20
17
16
12
5
8
9
1Y2
1Y3
1Y4
2Y0
2Y1
2Y2
2Y3
FBOUT
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TYPE
DESCRIPTION
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
Terminal Functions
TERMINAL
NAME NO.
Clock input. CLK provides the clock signal to be distributed by the CDC2509B clock driver. CLK is used
to provide the reference signal to the integrated PLL that generates the clock output signals. CLK must
CLK 24 I
FBIN 13 I
1G 11 I
2G 14 I
FBOUT 12 O
1Y (0:4) 3, 4, 5, 8, 9 O
2Y (0:3) 16, 17, 20, 21 O
AV
CC
AGND 1 Ground Analog ground. AGND provides the ground reference for the analog circuitry.
V
CC
GND 6, 7, 18, 19 Ground Ground
23 Power
2, 10, 15, 22 Power Power supply
have a fixed frequency and fixed phase for the PLL to obtain phase lock. Once the circuit is powered
up and a valid CLK signal is applied, a stabilization time is required for the PLL to phase lock the
feedback signal to its reference signal.
Feedback input. FBIN provides the feedback signal to the internal PLL. FBIN must be hard-wired to
FBOUT to complete the PLL. The integrated PLL synchronizes CLK and FBIN so that there is nominally
zero phase error between CLK and FBIN.
Output bank enable. 1G is the output enable for outputs 1Y(0:4). When 1G is low, outputs 1Y(0:4) are
disabled to a logic-low state. When 1G is high, all outputs 1Y(0:4) are enabled and switch at the same
frequency as CLK.
Output bank enable. 2G is the output enable for outputs 2Y(0:3). When 2G is low, outputs 2Y(0:3) are
disabled to a logic low state. When 2G is high, all outputs 2Y(0:3) are enabled and switch at the same
frequency as CLK.
Feedback output. FBOUT is dedicated for external feedback. It switches at the same frequency as CLK.
When externally wired to FBIN, FBOUT completes the feedback loop of the PLL. FBOUT has an
integrated 25-Ω series-damping resistor .
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 1Y(0:4) is enabled via the
1G input. These outputs can be disabled to a logic-low state by deasserting the 1G control input. Each
output has an integrated 25-Ω series-damping resistor.
Clock outputs. These outputs provide low-skew copies of CLK. Output bank 2Y(0:3) is enabled via the
2G input. These outputs can be disabled to a logic-low state by deasserting the 2G control input. Each
output has an integrated 25-Ω series-damping resistor.
Analog power supply . AVCC provides the power reference for the analog circuitry. In addition, A VCC can
be used to bypass the PLL for test purposes. When AVCC is strapped to ground, PLL is bypassed and
CLK is buffered directly to the device outputs.
CDC2509B
SCAS613 – SEPTEMBER 1998
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, AV
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 2) –0.5 V to 6.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Voltage range applied to any output in the high or low state,
VO (see Notes 2 and 3) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, I
IK
Output clamp current, I
Continuous output current, I
Continuous current through each VCC or GND ±100 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Maximum power dissipation at TA = 55°C (in still air) (see Note 4) 0.7 W. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. AVCC must not exceed VCC.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. This value is limited to 4.6 V maximum.
4. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
(see Note 1) AVCC < VCC +0.7 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
CC
(V
< 0) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
I
(V
OK
< 0 or VO > VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
(V
= 0 to VCC) ±50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
O
O
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
recommended operating conditions (see Note 5)
MIN MAX UNIT
VCC, AVCCSupply voltage 3 3.6 V
V
IH
V
IL
V
I
I
OH
I
OL
T
A
NOTE 5: Unused inputs must be held high or low to prevent them from floating.
High-level input voltage 2 V
Low-level input voltage 0.8 V
Input voltage 0 V
High-level output current –12 mA
Low-level output current 12 mA
Operating free-air temperature 0 70 °C
CC
V
†
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(INPUT)/CONDITION
(OUTPUT)
Clkin
100 MH
ps
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER TEST CONDITIONS VCC, AV
V
IK
V
OH
V
OL
I
I
§
I
CC
∆I
CC
C
i
C
‡
For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions.
§
For ICC of AVCC, and ICC vs Frequency (see Figures 7 and 8).
o
II = –18 mA 3 V –1.2 V
IOH = –100 µA MIN to MAX VCC–0.2
IOH = –12 mA 3 V 2.1
IOH = –6 mA 3 V 2.4
IOL = 100 µA MIN to MAX 0.2
IOL = 12 mA 3 V 0.8
IOL = 6 mA 3 V 0.55
VI = VCC or GND 3.6 V ±5 µA
VI = VCC or GND, IO = 0, Outputs: low or high 3.6 V 10 µA
One input at VCC – 0.6 V, Other inputs at VCC or GND 3.3 V to 3.6 V 500 µA
VI = VCC or GND 3.3 V 4 pF
VO = VCC or GND 3.3 V 6 pF
CC
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
f
clk
†
Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained, a
fixed-frequency , fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation delay, skew ,
and jitter parameters given in the switching characteristics table are not applicable. This parameter does not apply for input modulation under
SSC application.
Clock frequency 25 125 MHz
Input clock duty cycle 40% 60%
Stabilization time
†
MIN TYP‡MAX UNIT
V
V
MIN MAX UNIT
1 ms
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, C
PARAMETER
t
phase error
(see Notes 7 and 8,
Figures 3, 4, and 5)
t
sk(o)
Jitter
(see Figure 6)
Jitter
(see Figure 6)
Duty cycle F(clkin > 60 MHz) Any Y or FBOUT 45% 55%
t
r
t
f
‡
These parameters are not production tested.
§
The t
NOTES: 6. The specifications for parameters in this table are applicable only after any appropriate stabilization time has elapsed.
, – jitter
§
(pk-pk)
(cycle-cycle)
specification is only valid for equal loading of all outputs.
sk(o)
7. This is considered as static phase error.
8. Phase error does not include jitter. The total phase error is –230 ps to 230 ps for the 5% VCC range.
= 30 pF (see Note 6 and Figures 1 and 2)
L
FROM
CLKIN↑ = 66 MHz to100 MHz FBIN↑ –150 150 –200 200 ps
Any Y or FBOUT Any Y or FBOUT 200 ps
= 66 MHz to
z
TO
Any Y or FBOUT –80 80
Any Y or FBOUT |100|
Any Y or FBOUT 1.3 1.9 0.8 2.1 ns
Any Y or FBOUT 1.7 2.5 1.2 2.7 ns
‡
VCC, AVCC = 3.3 V
± 0.165 V
MIN TYP MAX MIN TYP MAX
VCC, AVCC = 3.3 V
± 0.3 V
UNIT
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
5
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
500
30 pF
W
Input
Output
3 V
50% V
CC
t
pd
t
r
0.4 V
2 V
50% V
CC
2 V
t
f
0.4 V
0 V
V
V
OH
OL
LOAD CIRCUIT FOR OUTPUTS
NOTES: A. CL includes probe and jig capacitance.
B. All input pulses are supplied by generators having the following characteristics: PRR ≤ 100 MHz, ZO = 50 Ω, tr ≤ 1.2 ns, tf≤ 1.2 ns.
C. The outputs are measured one at a time with one transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
CLKIN
FBIN
t
phase error
FBOUT
Any Y
t
sk(o)
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
Any Y
Any Y
t
sk(o)
Figure 2. Phase Error and Skew Calculations
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
PHASE ADJUSTMENT SLOPE AND PHASE ERROR
vs
LOAD CAPACITANCE
50
VCC = 3.3 V
40
fc = 100 MHz
CLY = 30pF
30
TA = 25°C
Phase Error Measured
20
from CLK to Y
10
Phase Error
250
200
150
100
50
0
–10
–20
–30
Phase Adjustment Slope – ps/pF
–40
–50
0 5 10 15 20 25 30 35 40
CLF – Lumped Feedback Capacitance at FBIN – pF
400
300
200
Phase Adjustment Slope
VCC = 3.3 V
CLY = CLF = 30 pF
TA = 25°C
Phase Error Measured
from CLK to FBIN
Figure 3
PHASE ERROR
vs
CLOCK FREQUENCY
45 50
0
–50
–100
–150
–200
–250
Phase Error – ps
100
Phase Error – ps
0
–100
35 45 55 65 75 85 95 105 115 125
NOTES: A. CLY = Lumped capacitive load at Y
B. CLF = Lumped feedback capacitance at FBIN
fc – Clock Frequency – MHz
Figure 4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
7
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
TYPICAL CHARACTERISTICS
PHASE ERROR
vs
SUPPLY VOLTAGE
400
fc = 100 MHz
350
CLY = CLF = 30 pF
TA = 25°C
300
Phase Error Measured
from CLK to FBIN
250
200
150
100
Phase Error – ps
50
0
–50
–100
2.9 3.0 3.1 3.2 3.3 3.4 3.5 3.6 3.7
VCC – Supply Voltage – V
Figure 5
ANALOG SUPPLY CURRENT
vs
CLOCK FREQUENCY
16
AVCC = 3.6 V
14
Bias = 0/3 V
CLY = CLF = 30 pF
12
TA = 25°C
JITTER
vs
CLOCK FREQUENCY
400
VCC = 3.3 V
350
300
250
200
Jitter – ps
150
100
50
Cycle to Cycle
0
35 45 55 65 75 85 95 105 115 125
fc – Clock Frequency – MHz
Peak to Peak
TA = 25°C
Figure 6
SUPPLY CURRENT
vs
CLOCK FREQUENCY
250
VCC = 3.6 V
Bias = 0/3 V
CLY = CLF = 30 pF
200
TA = 25°C
10
8
6
– Analog Supply Current – mA
4
CC
AI
2
0
10 20 40 60 80 100 120 140
fc – Clock Frequency – MHz
Figure 7
NOTES: A. CLY = Lumped capacitive load at Y
8
B. CLF = Lumped feedback capacitance at FBIN
150
100
– Supply Current – mA
CC
I
50
0
10 20 40 60 80 100 120 140
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
fc – Clock Frequency – MHz
Figure 8
CDC2509B
3.3-V PHASE-LOCK LOOP CLOCK DRIVER
SCAS613 – SEPTEMBER 1998
MECHANICAL INFORMATION
PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE
14 PIN SHOWN
0,65
14
1
1,20 MAX
A
7
0,05 MIN
0,30
0,19
8
6,60
4,50
4,30
6,20
M
0,10
Seating Plane
0,10
0,15 NOM
Gage Plane
0,25
0°–8°
0,75
0,50
PINS **
DIM
A MAX
A MIN
NOTES: A. All linear dimensions are in millimeters.
B. This drawing is subject to change without notice.
C. Body dimensions do not include mold flash or protrusion not to exceed 0,15.
D. Falls within JEDEC MO-153
8
3,10
2,90
14
5,10
4,90
16
5,10
20
6,60
6,404,90
24
7,90
7,70
28
9,80
9,60
4040064/E 08/96
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9
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Copyright 1998, Texas Instruments Incorporated
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