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CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
D
Low-Output Skew for Clock-Distribution
Applications
D
Differential Low-Voltage Pseudo-ECL
(LVPECL)-Compatible Inputs and Outputs
D
Distributes Differential Clock Inputs to Nine
Differential Clock Outputs
D
Output Reference Voltage, V
REF
, Allows
Distribution From a Single-Ended Clock
Input
D
Single-Ended LVPECL-Compatible Output
Enable
D
Packaged in Plastic Chip Carrier
description
The differential LVPECL clock-driver circuit
distributes one pair of differential LVPECL clock
Y8
Y8
Y7
V
CC0
Y7
Y6
Y6
NC – No internal connection
FN PACKAGE
(TOP VIEW)
REF
NCVCLKIN
4
321
5
6
7
8
9
10
11
13 14
12
Y5
Y5
CC
V
CLKINOEGND
28 27 26
15 16 17 18
Y4
Y4Y3Y3
CC0
V
25
24
23
22
21
20
19
Y0
Y0
Y1
V
Y1
Y2
Y2
CC0
inputs (CLKIN, CLKIN) to nine pairs of differential
clock (Y, Y
) outputs with minimum skew for clock
distribution. It is specifically designed for driving
50-Ω transmission lines.
When the output-enable (OE) is low, the nine dif ferential outputs switch at the same frequency as the differential
clock inputs. When OE is high, the nine differential outputs are in static states (Y outputs are in the low state,
Y outputs are in the high state).
The V
output can be strapped to the CLKIN input for a single-ended CLKIN input.
REF
The CDC111 is characterized for operation from 0°C to 70°C.
FUNCTION TABLE
INPUTS
CLKIN CLKIN OE Yn Yn
X X H L H
L HLLH
H LLHL
L V
H V
V
REF
V
REF
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
REF
REF
LLHL
H L L H
LL
LHL
OUTPUTS
H
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Copyright 1999, Texas Instruments Incorporated
1
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
logic diagram (positive logic)
CLKIN
CLKIN
OE
28
2
27
25
24
23
21
20
19
18
17
16
14
13
12
11
10
Y0
Y0
Y1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
9
Y7
7
Y7
6
Y8
5
Y8
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, VCC –0.5 V to 4.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input voltage range, VI (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output voltage range, VO (see Note 1) –0.5 V to VCC + 0.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input clamp current, IIK (VI < 0) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output clamp current, I
Continuous output current, IO (VO = 0 to VCC) –50 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Continuous current through VCC or GND
Maximum power dissipation at TA = 55°C (in still air) (see Note 2) 525 mW. . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Storage temperature range, T
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
2. The maximum package power dissipation is calculated using a juction temperature of 150_C and a board trace length of 750 mils.
For more information, refer to the
Book
, literature number SCBD002.
(VO < 0 or VO > VCC) –18 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
OK
–65°C to 150°C. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
stg
Package Thermal Considerations
application note in the
ABT Advanced BiCMOS T echnology Data
"
80 mA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
†
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
VIHHigh-level input voltage
VILLow-level input voltage
V
V
V
V
V
V
PARAMETER
MIN
MAX
UNIT
CLKIN, CLKIN
Y, Y
ps
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
recommended operating conditions (see Note 3)
MIN MAX UNIT
V
CC
T
A
f
clock
NOTE 3: VCC = V
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
Supply voltage 3 3.6 V
p
p
Operating free-air temperature 0 70 °C
Input frequency 500 MHz
CCO
PARAMETER TEST CONDITIONS MIN MAX UNIT
VCC = 3 V to 3.6 V VCC–1.38 VCC–1.26
VCC = 3.3 V 1.92 2.04
VCC = 3 V to 3.6 V VCC–1.025 VCC–0.88
VCC = 3.3 V 2.275 2.42
VCC = 3 V to 3.6 V VCC–1.81 VCC–1.62
VCC = 3.3 V 1.49 1.68
VI = 2.4 V, VCC = 3 .6 V 150 µA
IO = 0, VCC = 3 .6 V 80 mA
I
I
I
CC
REF
OH
OL
VCC = 3 V to 3.6 V VCC–1.165 VCC–0.88 V
VCC = 3.3 V 2.135 2.420 V
VCC = 3 V to 3.6 V VCC–1.81 VCC–1.475 V
VCC = 3.3 V 1.49 1.825 V
switching characteristics over recommended operating free-air temperature range,
V
= 3.3 V ± 0.3 V (see Figures 1 and 2)
CC
FROM TO
(INPUT) (OUTPUT)
t
PLH
t
PHL
t
PHL
t
sk(o)
t
sk(pr)
t
r
t
f
OE
Y, Y 900 ps
Y, Y 50 ps
Y, Y 150 ps
Y, Y 200 600 ps
Y, Y 200 600 ps
450 600
450 600
p
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
3
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
Y, Y
Outputs
From Output
Under Test
ZO = 50 Ω
VCC – 2 V
50 Ω
V
80%
80%
20%
t
r
t
f
20%
OH
V
OL
LOAD CIRCUIT
Waveform 1
OE
Y
Y
CLKIN
CLKIN
Outputs
t
PLH
t
PHL
VOLTAGE WAVEFORMS
RISE AND FALL TIMES
VCC – 0.9 V
VCC – 1.7 V
t
PLH
Y
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
50%
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
t
PHL
t
PLH
t
PHL
V
V
50%
OH
OL
VCC – 0.9 V
VCC – 1.7 V
V
OH
V
OL
NOTES: A. All input pulses are supplied by generators having the following characteristics: PRR ≤ 45 MHz, ZO = 50 Ω, tr ≤ 1 ns, tf≤ 1 ns.
B. Waveform 1 is for a Y
for a Y output with internal conditions such that the output is low except when disabled by the output control.
C. The outputs are measured one at a time with one transition per measurement.
output with internal conditions such that the output is high except when disabled by the output control, and
Figure 1. Load Circuit and Voltage Waveforms
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
PARAMETER MEASUREMENT INFORMATION
CLKIN
CLKIN
Y0
Y0
Y1
t
PLH1
t
PHL1
Y1
Y2
Y2
Y3
Y3
Y4
Y4
Y5
Y5
Y6
Y6
Y7
Y7
Y8
t
PLH2
t
PLH3
t
PLH4
t
PLH5
t
PLH6
t
PLH7
t
PLH8
t
PHL2
t
PHL3
t
PHL4
t
PHL5
t
PHL6
t
PHL7
t
PHL8
Y8
NOTES: A. Output skew, t
– The difference between the fastest and slowest t
– The difference between the fastest and slowest t
B. Process skew, t
– The difference between the fastest and slowest t
– The difference between the fastest and slowest t
PLHn
PHLn
PLHn
PHLn
t
PHL9
t
PLH9
, is calculated as the greater of:
sk(o)
, is calculated as the greater of:
sk(pr)
Figure 2. Waveforms for Calculation of t
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
(n = 1, 2,...9)
(n = 1, 2
(n = 1, 2,...9)
(n = 1, 2, . .. 9) across multiple devices
,...9)
sk(o)
, t
sk(pr)
5
CDC111
1-LINE TO 9-LINE DIFFERENTIAL LVPECL CLOCK DRIVER
SCAS321G – SEPTEMBER 1993 – REVISED AUGUST 1999
MECHANICAL DATA
FN (S-PQCC-J**) PLASTIC J-LEADED CHIP CARRIER
20 PIN SHOWN
Seating Plane
0.004 (0,10)
D
D1
13
4
E1E
8
9
NO. OF
PINS
**
D/E
19
13
18
14
0.032 (0,81)
0.026 (0,66)
0.050 (1,27)
0.008 (0,20) NOM
D1/E1
MINMAXMIN
MAX
D2/E2
MIN
0.180 (4,57) MAX
0.120 (3,05)
0.090 (2,29)
0.020 (0,51) MIN
D2/E2
D2/E2
0.021 (0,53)
0.013 (0,33)
0.007 (0,18)
MAX
M
20
28
44
52
68
84
NOTES: A. All linear dimensions are in inches (millimeters).
B. This drawing is subject to change without notice.
C. Falls within JEDEC MS-018
6
0.385 (9,78)
0.485 (12,32)
0.685 (17,40)
0.785 (19,94)
0.985 (25,02)
1.185 (30,10)
0.395 (10,03)
0.495 (12,57)
0.695 (17,65)
0.795 (20,19)
0.995 (25,27)
1.195 (30,35)
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
0.350 (8,89)
0.450 (11,43)
0.650 (16,51)
0.750 (19,05)
0.950 (24,13)
1.150 (29,21)
0.356 (9,04)
0.456 (11,58)
0.656 (16,66)
0.756 (19,20)
0.958 (24,33)
1.158 (29,41)
0.141 (3,58)
0.191 (4,85)
0.291 (7,39)
0.341 (8,66)
0.441 (11,20)
0.541 (13,74)
0.169 (4,29)
0.219 (5,56)
0.319 (8,10)
0.369 (9,37)
0.469 (11,91)
0.569 (14,45)
4040005/B 03/95
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty . Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOL VE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICA TIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
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