Texas Instruments CD74HCT652M96, CD74HCT652M, CD74HC652EN Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS194

[ /Title (CD74HC652, CD74HCT652)
/Subject (High-Speed CMOS Logic Octal-Bus Trans­ceiver/Registers, Three-State)
/Author ()
/Keywords ()
/Creator ()
/DOCINFO pdfmark

[ /PageMode /UseOutlines
/DOCVIEW pdfmark

Features

• CD74HC652, CD74HCT652 . . . . . . . . . . . Non-Inverting

• Independent Registers for A and B Buses

• Three-State Outputs

• Drives 15 LSTTL Loads

• Typical Propagation Delay = 12ns at V

CC

=5V,CL= 15pF

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

C to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• Alternate Source is Philips

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

IL

= 30%, NIH = 30% of V

CC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

IL

= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, I

l

≤ 1µA at VOL, V

OH

Pinout

CD74HC652, CD74HCT652

(PDIP, SOIC)

TOP VIEW

1
2
3
4
5
6
7
8

9
10
11
12

CAB
SAB

OE

AB

A0
A1
A2
A3
A4
A5
A6
A7

GND

16

17

18

19

20

21

22

23

24

15
14
13

V

CC

SBA
OE

BA

B0
B1

B3

B5
B6
B7

CBA

B2

B4

February 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

File Number 2229.2

CD74HC652,

CD74HCT652

High-Speed CMOS Logic

Octal-Bus Transceiver/Registers, Three-State

2

Description

The Harris CD74HC652 and CD74HCT652 three-state, octal­bus transceiver/registers use silicon-gate CMOS technology
to achieve operating speeds similar to LSTTL with the low
power consumption of standard CMOS integrated circuits.
The CD74HC652 and CD74HCT652 have non-inverting
outputs. These devices consists of bus transceiver circuits, D­type flip-flops, and control circuitry arranged for multiplexed
transmission of data directly from the data bus or from the
internal storage registers. Output Enables OE

AB

and OE

BA

are provided to control the transceiver functions. SAB and
SBA control pins are provided to select whether real-time or
stored data is transferred. The circuitry used for select control
will eliminate the typical decoding glitch that occurs in a
multiplexer during the transition between stored and real-time
data. A LOW input level selects real-time data, and a HIGH
selects stored data. The following examples demonstrates the
four fundamentals bus-management functions that can be
performed with the octal-bus transceivers and registers.

Data on the A or B data bus, or both, can be stored in the
internal D flip-flops by low-to-high transitions at the appropriate
clock pins (CAB or CBA) regardless of the select of the control
pins. When SAB and SBA are in the real-time transfer mode, it
is also possible to store data without using the D-type flip-flops
by simultaneously enabling OE

AB

and OEBA. In this
configuration, each output reinforces its input. Thus, when all
other data sources to the two sets of bus lines are at high
impedance, each set of bus lines will remain at its last state.

Ordering Information

PART NUMBER

TEMP. RANGE

(oC) PACKAGE

PKG.

NO.

CD74HC652EN -55 to 125 24 Ld PDIP E24.3
CD74HCT652M -55 to 125 24 Ld SOIC M24.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

CD74HC652, CD74HCT652CD74HC652, CD74HCT652

3

CD74HC652, CD74HCT652

Functional Diagram

FUNCTION TABLE

INPUTS DATA I/O OPERATION OR FUNCTION

OE

AB

OE

BA

CAB CBA SAB SBA A0 THRU A7 B0 THRU B7 651 652

L H H or L H or L X X Input Input Isolation (Note 3) Isolation (Note 3)
LH↑↑X X Store A and B Data Store A and B Data
XH↑H or L X X Input Unspecified

(Note 4)

Store A, Hold B Store A, Hold B

HH↑↑X

(Note 5)

X Input Output Store A in Both

Registers

Store A in Both

Registers

L X H or L ↑ X X Unspecified

(Note 4)

Input Hold A, Store B Hold A, Store B

LL↑↑XX

(Note 5)

Output Input Store B in Both

Registers

Store B in Both

Registers

L L X X X L Output Input Real-Time B Data to

A Bus

Real-TimeBData to

A Bus

L L X H or L X H Stored B Data to A

Bus

Stored B Data to A

Bus

20

19

18

17

15

13

14

16

4

B0

B1

B2

B3

B4

B5

B6

B7

OE

BA

OE

AB

21

3

6

11

5

7

8

9

10

A0

A1

A2

A3

A4

A5

A6

A7

1

23

2

22

CAB CLOCK

CBA CLOCK
SAB SOURCE
SBA SOURCE

GND = PIN 12
V

CC

= PIN 24

B
DATA
PORT

A
DATA
PORT

FLIP-FLOP

CLOCKS

DATA

SOURCE

SELECTION

INPUTS

4

H H X X L X Input Output Real-Time A Data to

B Bus

Real-TimeA Datato

B Bus

H H H or L X H X Stored A Data to B

Bus

Stored A Data to B

Bus

H L H or L H or L H H Output Output Stored A Data to B

Bus and

Stored A Data to B

Bus

Stored B Data to A

Bus

Stored B Data to A

Bus

NOTES:

3. To prevent excess currents in the High-Z (isolation) modes, all I/O terminals should be terminated with 10kΩ to 1MΩ resistors.

4. The data output functions may be enabled or disabled by various signals at the OE

AB

or OEBAinputs. Data input functions are always

enabled; i.e., data at the bus pins will be stored on every low-to-high transition on the clock inputs.

5. Select Control = L: Clocks can occur simultaneously.
Select Control = H: Clocks must be staggered in order to load both registers.

FUNCTION TABLE

INPUTS DATA I/O OPERATION OR FUNCTION

OE

AB

OE

BA

CAB CBA SAB SBA A0 THRU A7 B0 THRU B7 651 652

CD74HC652, CD74HCT652CD74HC652, CD74HCT652