Texas Instruments CD74HCT564M, CD74HCT564E, CD74HCT534E, CD74HC534E, CD74HC564M Datasheet

CD74HC534, CD74HCT534,

[ /Title
(CD74
HC534
,
CD74
HCT53
4,
CD74
HC564
,
CD74
HCT56

Data sheet acquired from Harris Semiconductor
SCHS188

High Speed CMOS Logic Octal D-Type Flip-Flop,

January 1998

Features

• Buffered Inputs

• Common Three-State Output-Enable Control

• Three-State Outputs

• Bus Line Driving Capability

• Typical Propa gation Delay = 13ns at V
C

= 15pF, TA = 25oC (Clock to Output)

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

CC

= 5V,

o

CD74HC564, CD74HCT564

Three-State Inverting Positive-Edge Triggered

Description

The Harris CD74HC534, CD74HCT534, CD74HC564 and
CD74HCT564 are high speed Octal D-Type Flip-Flops manu­factured with silicon gate CMOS technology. The y possess
the low power consumption of standard CMOS integrated cir­cuits, as well as the ability to drive 15 LSTTL loads. Due to the
large output drive capability and the three-state feature, these
devices are ideally suited for interfacing with bus lines in a bus
organized system. The two types are functionally identical and
differ only in their pinout arrangements.

The CD74HC534, CD74HCT534, CD74HC564 and
CD74HCT564 are positive edge triggered flip-flops. Data at
the D inputs, meeting the setup and hold time requirements,

C to 125oC

OH

are inverted and transferred to the Q outputs on the positive
going transition of the CLOCK input. When a high logic level is
applied to the OUTPUT ENABLE input, all outputs go to a
high impedance state, regardless of what signals are present
at the other inputs and the state of the storage elements.

The CD74HCT logic family is speed, function, and pin
compatible with the standard 74LS logic family.

Ordering Information

CC

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC534E -55 to 125 20 Ld PDIP E20.3
CD74HCT534E -55 to 125 20 Ld PDIP E20.3
CD74HC564E -55 to 125 20 Ld PDIP E20.3
CD74HCT564E -55 to 125 20 Ld PDIP E20.3
CD74HC564M -55 to 125 20 Ld SOIC M20.3
CD74HCT564M -55 to 125 20 Ld SOIC M20.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

PKG.

NO.

Pinouts

CD74HC534, CD74HCT534 (PDIP)

OE

Q0
D0
D1
Q1
Q2
D2
D3
Q3

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1
2
3
4
5
6
7
8
9

10

TOP VIEW

V

20

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

CP 11

1

CD74HC564, CD74HCT564 (PDIP, SOIC)

1

OE

D0

2

D1

3

D2

4

D3

5

D4

6

D5

7
8

D6

9

D7

GND

10

TOP VIEW

V

20

CC

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13
12

Q7
CP

File Number 1640.1

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Functional Diagram

CP

OE

D

0

D

D

1

Q

CP CP CP CP CP CP CP CP

Q

0

D

2

Q

D

Q

1

D

3

Q

D

Q

2

D

4

Q

D

Q

3

D

5

Q

D

D

Q

4

D

6

Q

Q

Q

D

5

TRUTH TABLE

INPUTS OUTPUT

OE CP Dn Qn

L ↑ HL
L↑LH
L L X No Change

HXXZ

NOTE:
H = High Level (Steady State)
L = Low Level (Steady State)
X = Don’t Care
↑ = Transition from Low to High Level
Z = High Impedance State

D

7

Q

D

Q

6

O

7

2

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

3

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

Current

V

or VIHVO=V

IL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

Additional Quiescent
Device Current Per

I

I

I

CC

V

or VIHVO=V

IL

∆I

CC

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

0 6 - - 8 - 80 - 160 µA

GND

CC

-6--±0.5 - ±5.0 - ±10 µA

or GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

6 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

CC

- 5.5 - - ±0.5 - ±5.0 - ±10 µA

or GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

D0 - D7 0.15

CP 0.30
OE 0.55

NOTE: Unit load is ∆ICClimit specific in DC Electrical Specifications
Table, e.g., 360µA max. at 25oC.

4

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Maximum Clock

f

MAX

Frequency

Clock Pulse Width t

Setup Time

W

t

SU

Data to Clock

Hold Time

t

H

Data to Clock

HCT TYPES

Maximum Clock

f

MAX

Frequency

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

2 6 - - 5 - - 4 - - MHz

4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20- -ns
260- -75- -90- -ns

4.5 12 - - 15 - - 18 - - ns
610- -13- -15- -ns
25--5--5--ns

4.5 5 - - 5 - - 5 - - ns
65--5--5--ns

4.5 25 - - 20 - - 16 - - MHz

Clock Pulse Width t
Setup Time

W

t

SU

4.5 20 - - 25 - - 30 - - ns

4.5 20 - - 25 - - 30 - - ns

Data to Clock
Hold Time

t

H

4.5 5 - - 5 - - 5 - - ns

Data to Clock (534)
Hold Time

t

H

4.5 3 - - 3 - - 3 - - ns

Data to Clock (564)

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS VCC(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

HC TYPES

Propagation Delay t

PLH

, t

PHLCL

= 50pF

Clock to Output 2 - - 165 - 205 - 250 ns

4.5 - - 33 - 41 - 50 ns

C

= 15pF 5 - 13 - - - - - ns

L

C

= 50pF 6 - - 28 - 35 - 43 ns

L

Output Disable to Q (534) t

PLZ,tPHZCL

= 50pF 2 - - 150 - 190 - 225 ns

4.5 - - 30 - 38 - 45 ns

C

= 15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 26 - 33 - 38 ns

L

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Switching Specifications C

PARAMETER SYMBOL

Output Disable to Q (564) t

= 50pF, Input tr, tf= 6ns (Continued)

L

TEST

CONDITIONS VCC(V)

PLZ,tPHZCL

= 50pF 2 - - 135 - 170 - 205 ns

25

o

C

-40oC TO
85oC

-55oC TO
125oC

4.5 - - 27 - 34 - 41 ns

C

= 15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 23 - 29 - 35 ns

L

Output Enable to Q t

PZL,tPZHCL

= 50pF 2 - - 150 - 190 - 225 ns

4.5 - - 30 - 38 - 45 ns

C

= 15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 26 - 33 - 38 ns

L

Maximum Clock Frequency f
Output Transition Time t

THL

MAX

, t

CL = 15pF 5 - 60 - - - - - MHz

TLHCL

= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns

Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

C

(Notes 4, 5)

I

C

O

PD

CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

- 5 -32- - - - - pF

HCT TYPES

Propagation Delay t

PHL,tPLH

Clock to Output CL = 50pF 4.5 - - 35 - 44 - 53 ns

C

= 15pF 5 - 14 - - - - - ns

L

Output Disable to Q t

Output Enable to Q t

Maximum Clock Frequency f

Output Transition Time

PLZ,tPHZCL

PZL,tPZHCL

MAX

t

TLH

Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

C

(Notes 4, 5)

, t

THLCL

I

C

O

PD

= 50pF 4.5 - - 30 - 38 - 45 ns

C

= 15pF 5 - 12 - - - - - ns

L

= 50pF 4.5 - - 35 - 44 - 53 ns

C

= 15pF 5 - 14 - - - - - ns

L

CL = 15pF 5 - 50 - - - - - MHz

= 50pF 4.5 - - 12 - 15 - 18 ns

CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

- 5 -36- - - - - pF

NOTES:

4. C

is used to determine the dynamic power consumption, per package.

PD

5. PD=CPDV

CC

2

fi+ ∑ CLV

2

fOwhere fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC= Supply

CC

Voltage.

UNITSMIN TYP MAX MIN MAX MIN MAX

6

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

fC

50%

1.3V

I

fC

L

3V

GND

+ tWH=

t

t

WH

WL

I

L

V

CC

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

THL

90%
50%
10%

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 3. HCTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

tr = 6ns

INPUT

t

THL

2.7V

1.3V

0.3V

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 4. HCTTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V

SET, RESET

1.3V

90%

1.3V
t

t

PLH

TLH

90%

1.3V
10%

t

PHL

t

THL

OR PRESET

IC

C

L

50pF

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

GND

CD74HC534, CD74HCT534, CD74HC564, CD74HCT564

Test Circuits and Waveforms

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

90%

10%

90%

OUTPUTS

DISABLED

(Continued)

10%

t

PZL

t

PZH

FIGURE 7. HCTHREE-STATE PROPAGATION DELAY

WAVEFORM

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

50%

50%

OUTPUTS
ENABLED

IC WITH

THREE-

STATE

OUTPUT

V

CC

GND

OUTPUT
R

0.3

t

t

6ns

PZL

PZH

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

3V

GND

1.3V

1.3V
OUTPUTS

ENABLED

NOTE: Opendrain waveformst
VCC, CL = 50pF.

FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

and t

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

PZL

8

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