Texas Instruments CD74HCT4020E, CD74HCT4020M96, CD74HCT4020M, CD74HC4020M96, CD74HC4020M Datasheet
...
CD74HC4020,
/
j
[ /Title
(CD74
HC402
0,
CD74
HCT40
20)
Subect
(High
Speed
CMOS
Data sheet acquired from Harris Semiconductor
SCHS201
February 1998
Features
• Fully Static Operation
• Buffered Inputs
• Common Reset
• Negative Edge Clocking
• Typical f
T
= 25oC
A
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 60 MHz at VCC = 5V, CL = 15pF,
MAX
= 30%, NIH = 30% of V
IL
o
C to 125oC
CC
CD74HCT4020
High Speed CMOS Logic
14-Stage Binary Counter
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
Description
The Harris CD74HC4020 and CD74HCT4020 are 14-stage
ripple-carry binary counters. All counter stages are masterslave flip-flops. The state of the stage advances one count
on the negative clock transition of each input pulse; a high
voltage level on the MR line resets all counters to their zero
state. All inputs and outputs are buffered.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC4020E -55 to 125 16 Ld PDIP E16.3
CD74HCT4020E -55 to 125 16 Ld PDIP E16.3
≤ 1µA at VOL, V
l
OH
PKG.
NO.
Pinout
CD74HC4020, CD74HCT4020
(PDIP, SOIC)
TOP VIEW
16
Q
Q
Q
Q6
Q
Q
Q
GND
1
12
2
13
3
14
4
5
5
6
7
7
4
8
V
Q
15
14
Q
13
Q
12
Q
11
MR
10
CP
Q
9
CC
11
10
8
9
‘
1
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1484.2
Functional Diagram
CD74HC4020, CD74HCT4020
V
CC
16
10
INPUT
PULSES
14-STAGE
RIPPLE
COUNTER
11
MASTER
RESET
GND
9
Q1’
7
Q4
5
Q5
4
Q6
6
Q7
13
Q8
12
Q9
14
Q10
15
Q11
1
Q12
2
Q13
3
Q14
8
TRUTH TABLE
BUFFERED
OUTPUTS
CP COUNT MR OUTPUT STATE
↑ L No Change
↓ L Advance to Next State
X H All Outputs Are Low
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care,
↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
2
Logic Diagram
CD74HC4020, CD74HCT4020
3
Q
R
14
CP Q
CP
Q
R
13
CP Q
CP
Q
R
12
CP Q
CP
Q
R
11
CP Q
CP
Q
R
10
CP Q
CP
Q
9
CP Q
CP Q
CP Q
CP Q
CP Q
CP Q
R
CP
Q
8
R
CP
Q
7
R
CP
Q
6
R
CP
Q
5
R
CP
Q
4
R
CP
2
1
15
14
12
13
6
4
5
7
14
Q
13
Q
12
Q
11
Q
10
Q
9
Q
8
Q
7
Q
6
Q
5
Q
4
Q
Q
3
CP Q
CP Q
CP Q
10
CP
R
CP
Q
2
R
CP
Q
Q’
I
R
CP
11
MR
9
’
1
Q
3
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