Texas Instruments CD74HCT299M, CD74HCT299E, CD74HC299M96, CD74HC299M, CD74HC299E Datasheet

Data sheet acquired from Harris Semiconductor

/
j

SCHS178

January 1998

CD74HC299,

CD74HCT299

High Speed CMOS Logic

8-Bit Universal Shift Register; Three-State

[ /Title
(CD74
HC299
,
CD74
HCT29

9)
Sub­ect

(High
Speed
CMOS
Logic
8-Bit
Uni­versal
Shift

Features

• Buffered Inputs

• Four Operating Modes: Shift Left, Shift Right, Load
and Store

• Can be Cascaded for N-Bit Word Lengths

- I/O7 Bus Drive Capability and Three-State for

• I/O

0

Bus Oriented Applications

• Typical f

= 50MHz at VCC=5V,CL= 15pF, TA=25oC

MAX

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

C to 125oC

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

OH

Pinout

CD74HC299, CD74HCT299

(PDIP, SOIC)

TOP VIEW

S0
OE1
OE2

I/O
I/O
I/O
I/O

Q0

MR

GND

1
2
3
4

6

5

4

6

2

7

0

8
9

10

V

20

CC

S1

19

DS7

18

Q7

17

I/O

16

7

I/O

15

5

I/O

14

3

I/O

13

1

12

CP
DS0

11

Description

The Harris CD74HC259 and CD74HCT299 are 8-bit
shift/storage registers with three-state bus interface
capability. The register has four synchronous-operating
modes controlled by the two select inputs as shown in the
mode select (S0, S1) table. The mode select, the serial data
(DS0, DS7) and the parallel data (I/O

- I/O7) respond only

0

to the low-to-high transition of the clock (CP) pulse. S0, S1
and data inputs must be one set-up time prior to the clock
positive transition.

The Master Reset (
When

MR output is low, the register is cleared regardless of

MR) is an asynchronous active low input.

the status of all other inputs. The register can be expanded
by cascading same units by tying the serial output (Q0) to
the serial data (DS7) input of the preceding register, and
tying the serial output (Q7) to the serial data (DS0) input of
the following register. Recirculating the (n x 8) bits is
accomplished by tying the Q7 of the last stage to the DS0 of
the first stage.

The three-state input/output I(/O) port has three modes of
operation:

CC

1. Both output enable (

OE1andOE2)inputs are lowandS0
or S1 or both are low, the data in the register is presented
at the eight outputs.

2. When both S0 and S1 are high, I/O terminalsare in the
high impedance state butbeing input ports, readyforpar­allel data to be loaded into eight registers with one clock
transition regardless of the status of

OE1 and OE2.

3. Either one of the two output enable inputs being high will
force I/O terminals to be in the off-state. It is noted that
each I/O terminal is a three-state output and a CMOS
buffer input.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC299E -55 to 125 20 Ld PDIP E20.3
CD74HCT299E -55 to 125 20 Ld PDIP E20.3
CD74HC299M -55 to 125 20 Ld SOIC M20.3
CD74HCT299M -55 to 125 20 Ld SOIC M20.3

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1485.1

Functional Diagram

CD74HC299, CD74HCT299

CP OE1 OE2 MR

12 2 3 9

THREE-

STATE

CONTROL

20

V

CC

BUS LINE

OUTPUTS

STANDARD

OUTPUT

I/O
I/O
I/O
I/O

Q0
S0

7

0

6

2

5

4

4

6

8
1

I/O

THREE-STATE

OUTPUTS

10 11 18

GND

SHIFT

REGISTER

MODE SELECTION

DS0 DS7

I/O

THREE-STATE

OUTPUTS

13

I/O

14

I/O

15

I/O

16

I/O

17

Q7

19

S1

1
3

BUS LINE
OUTPUTS

5
7

STANDARD
OUTPUT

MODE SELECT FUNCTION TABLE THREE-STATE I/O PORT OPERATING MODE

INPUTS INPUTS/OUTPUTS

FUNCTION

OE1 OE2 S0 S1 Qn (REGISTER) I/O0 --- I/O7

Read Register L L L X L L

L

LL

XH H
LLXL L L
LLXL H H

Load Register X X H H Qn = I/On I/On = Inputs
Disable I/O H X X X X (Z)

X H X X X (Z)

TRUTH TABLE

INPUTS REGISTER OUTPUTS

FUNCTION

MR CP S0 S1 DS0 DS7 I/On Q0 Q1 --- Q6 Q7

RESET (CLEAR) L XXXXXXLL---LL

Shift Right H ↑ hllXXLq

H ↑ hlhXXHq

Shift Left H ↑ lhXlXq

H ↑ lhXhXq

Hold (Do Nothing) H ↑ l l XXXq

q2 --- q

1

q

1

q

0

0

0

2

1

--- q

--- q

--- q

--- q

q

5

5

7

7

6

Q6

H

q

6

L

7

Parallel Load H ↑ hhXXlLL---LL

H↑h h X X h H H --- H H

NOTE: H = Input Voltage High Level, h = Input voltage high one set-up timer prior clock transition; L = Input Voltage Low Level; l = Input
voltage low one set-up time prior clock transition; qn = Lower case letter indicates the state of the reference output one set-up time prior to
clock transition; X - Voltage level on logic status don’t care; Z = Output in high impedance state, ↑ = Low to High Clock Transition.

2

CD74HC299, CD74HCT299

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, IO,For -0.5V < VO < VCC + 0.5V

For Q Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

For I/O Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

V

OH

OL

I

VIHor V

VIHor V

VCC or

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

4.5 4.4 - - 4.4 - 4.4 - V
6 5.9 - - 5.9 - 5.9 - V

Qn I/On ----- - - - V

-4 -6 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 -7.8 6 5.48 - - 5.34 - 5.2 - V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

4.5 - - 0.1 - 0.1 - 0.1 V
6 - - 0.1 - 0.1 - 0.1 V

Qn I/On ----- - - - V

4 6 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 7.8 6 - - 0.26 - 0.33 - 0.4 V

-6--±0.1 - ±1-±1µA

GND

UNITSV

3

CD74HC299, CD74HCT299

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three- State Leak-

age Current

V

or VIHVO=V

IL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three- State Leak­age Current

Additional Quies­cent Device Cur-

I

I

I

CC

V

or VIHVO=V

IL

∆I

CC

rent Per
Input Pin: 1 Unit
Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

0 6 - - 8 - 80 - 160 µA

GND

CC

-6--±0.5 - ±5-±10 µA

or GND

- - 4.5 to

- - 4.5 to

VIHor V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

IL

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

CC

-6--±0.5 - ±5-±10 µA

or GND

V

CC

- 4.5to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

S1, MR 0.25

I/O0 - I/O

7

DS0, DS7 0.25

S0, CP 0.6

OE1, OE2 0.3

NOTE: Unit load is ∆ICClimit specific in Static Specifications Table,
e.g., 360µA max. at 25oC.

0.25

4

CD74HC299, CD74HCT299

Prerequisite for Switching Specifications

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC(V)

HC TYPES

Maximum Clock

f

MAX

Frequency

MR Pulse Width t

Clock Pulse Width t

Setup Time

W

W

t

SU

DS0, DS7, I/On to Clock

Hold Time DS0, DS7,

t

H

I/On, S0, S1 to Clock

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

2 6 - - 5 - - 4 - - MHz

4.5 30 - - 25 - - 20 - - MHz
6 35 - - 29 - - 23 - - MHz
250- -65- -75--ns

4.5 10 - - 13 - - 15 - - ns
6 9 - - 11 - - 13 - - ns
2 80 - - 100 - - 120 - - ns

4.5 16 - - 20 - - 24 - - ns
614- -17- -20--ns
2 100 - - 125 - - 150 - - ns

4.5 20 - - 25 - - 30 - - ns
617- -21- -26--ns
20--0--0--ns

4.5 0 - - 0 - - 0 - - ns
60--0--0--ns

Recovery Time
MR to Clock

Setup Time
S1, S0 to Clock

HCT TYPES

Maximum Clock
Frequency

MR Pulse Width t
Clock Pulse Width t
Setup Time DS0, DS7,

I/On, S0, S1 to Clock
Hold Time DS0, DS7,

I/On, S0, S1 to Clock
Recovery Time MR to

Clock
Setup Time S1, S0 to

Clock

t

REC

t

f

MAX

t

t

REC

t

SU

W

W

SU

t

SU

25--5--5--ns

4.5 5 - - 5 - - 5 - - ns
65--5--5--ns
2 120 - - 150 - - 180 - - ns

4.5 24 - - 30 - - 36 - - ns
620- -26- -31--ns

4.5 25 - - 20 - - 16 - - ns

4.5 15 - - 19 - - 22 - - ns

4.5 20 - - 25 - - 30 - - ns

4.5 20 - - 25 - - 30 - - ns

H

4.5 0 - - 0 - - 0 - - ns

4.5 5 - - 5 - - 5 - - ns

4.5 27 - - 34 - - 41 - - ns

5

CD74HC299, CD74HCT299

Switching Specifications C

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

Clock to I/O Output,
Clock to Q0 and Q7,
MR to Output

Output Enable and Disable
Times

Output High-Z to High Level t

Output High Level to High-Z t

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS V

PLH

t

PZH

, t

PHLCL

t

PZL

, t

PLZ

t

PHZ
PZH

PHZ

= 50pF

= 15pF 5 - 17 - - - - - ns

C

L

C

= 50pF 6 - - 34 - 43 - 51 ns

L

CL = 15pF 5 - 10 - - - - - ns

CL = 50pF 2 - - 155 - 195 - 235 ns

CL = 50pF 2 - - 185 - 230 - 280 ns

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

2 - - 200 - 250 - 300 ns

4.5 - - 40 - 50 - 60 ns

-13- - - - - ns

-15- - - - - ns

4.5 - - 31 - 39 - 47 ns
6 - - 26 - 33 - 40 ns

4.5 - - 37 - 46 - 56 ns
6 - - 31 - 39 - 48 ns

Output Low Level to High-Z t

PLZ

CL = 50pF 2 - - 155 - 195 - 235 ns

4.5 - - 31 - 39 - 47 ns
6 - - 26 - 33 - 40 ns

Output High-Z to Low Level t

PZL

CL = 50pF 2 - - 130 - 165 - 195 ns

4.5 - - 26 - 33 - 39 ns
6 - - 22 - 28 - 33 ns

Output Transition Time t

THL

, t

TLHCL

= 50pF

Q0, Q7 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

I/O0 to I/O

7

t

THL

, t

TLHCL

= 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns

Input Capacitance C
Three-State Output

C

I

O

CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

Capacitance
Power Dissipation Capacitance

(Notes 4, 5)

C

PD

CL = 15pF 5 - 150 - - - - - pF

6

CD74HC299, CD74HCT299

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns (Continued)

L

TEST

CONDITIONS V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

HCT TYPES

Propagation Delay t

Clock to I/O Output,
Clock to Q0 and Q7

MR to Output t
Output Enable and Disable

Times
Output High-Z to High Level t
Output High Level to High-Z t
Output Low Level to High-Z t
Output High-Z to Low Level t

Output Transition Time t

PHL,tPLH

PHL,tPLH

t

PZL,tPZH

t

, t

PLZ

PHZ
PZH
PHZ

PLZ
PZL

, t

TLH

THL

CL = 50pF 4.5 - - 45 - 56 - 68 ns
C

= 15pF 5 - 19 - - - - - ns

L

CL = 50pF 4.5 - - 46 - 58 - 69 ns

,

CL = 15pF 5 - 10,

--- - -ns

13, 15
CL = 50pF 4.5 - - 32 - 40 - 48 ns
CL = 50pF 4.5 - - 37 - 46 - 56 ns
CL = 50pF 4.5 - - 32 - 40 - 48 ns
CL = 50pF 4.5 - - 30 - 38 - 45 ns

Q0, Q7 CL = 50pF 4.5 - - 15 - 19 - 22 ns

to I/O

I/O

0

7

Input Capacitance C
Three-State Output

Capacitance

IN

C

O

CL = 50pF 4.5 - - 12 - 15 - 18 ns
CL = 50pF - 10 - 10 - 10 - 10 pF

- - 20 - 20 - 20 - 20 pF

UNITSMIN TYP MAX MIN MAX MIN MAX

Power Dissipation Capacitance

C

PD

CL = 15pF 5 - 170 - - - - - pF

(Notes 4, 5)

NOTES:

4. C

is used to determine the dynamic power consumption, per register.

PD

5. PD=CPDV

CC

2

fi+ ∑ (CLV

2

fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance,

CC

VCC = Supply Voltage.

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. Forf

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

fC

50%

I

L

V

CC

GND

1.3V

I

fC

L

3V

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

t

fCL

t

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. Forf

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

7

CD74HC299, CD74HCT299

Test Circuits and Waveforms

(Continued)

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

90%
50%
10%

THL

90%

t

50%

10%

PLH

INVERTING

OUTPUT

t

PHL

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tfC

L

50%

t

H(L)

t

SU(L)

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

V

CC

GND

V

CC

50%
GND

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

3V

GND

3V

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

1.3V

90%

1.3V
t

IC

t

PLH

TLH

t

THL

90%

1.3V
10%

t

PHL

GND

C

L

50pF

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

8

CD74HC299, CD74HCT299

Test Circuits and Waveforms

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

90%

10%

90%

OUTPUTS

DISABLED

(Continued)

10%

t

PZL

t

PZH

FIGURE 7. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

50%

50%

OUTPUTS
ENABLED

IC WITH

THREE-

STATE

OUTPUT

V

CC

GND

R

OUTPUT

0.3

t

t

6ns

PZL

PZH

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

3V

GND

1.3V

1.3V
OUTPUTS

ENABLED

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

and t

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

PZL

9

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