Texas Instruments CD74HCT273M96, CD74HCT273M, CD74HCT273E, CD74HC273SM, CD74HC273M96 Datasheet

CD74HC273,

/
j

[ /Title
(CD74
HC273
,
CD74
HCT27

3)
Sub­ect

(High
Speed
CMOS
Logic
Octal
D­Type
Flip-

Data sheet acquired from Harris Semiconductor
SCHS174

February 1998

Features

• Common Clock and Asynchronous Master Reset

• Positive Edge Triggering

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

CC

OH

CD74HCT273

High Speed CMOS Logic

Octal D-Type Flip-Flop with Reset

Description

The Harris CD74HC273 and CD74HCT273 high speed octal
D-Type flip-flops with a direct clear input are manufactured
with silicon-gate CMOS technology . They possess the low
power consumption of standard CMOS integrated circuits.

Information at the D inputis transferred to the Q outputs on
the positive-going edge of the clock pulse. All eight flip-flops
are controlled by a common clock (CP) and a common reset
(

MR). Resetting is accomplished by a low voltage level
independent of the clock. All eight Q outputs are reset to a
logic 0.

Ordering Information

TEMP.RANGE

PART NUMBER

CD54HC273F -55 to 125 20 Ld CERDIP F20.3

CD54HCT273F -55 to 125 20 Ld CERDIP F20.3

CD74HC273E -55 to 125 20 Ld PDIP E20.3

CD74HCT273E -55 to 125 20 Ld PDIP E20.3

CD74HC273M -55 to 125 20 Ld SOIC M20.3

CD74HCT273M -55 to 125 20 Ld SOIC M20.3
NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

Pinout

CD54HC273, CD54HCT273, CD74HC273, CD74HCT273

(PDIP, SOIC, CERDIP)

TOP VIEW

1

MR

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

V

20

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4
CP

11

File Number 1479.2

Functional Diagram

CD74HC273, CD74HCT273

CLOCK

CP

DAT A

INPUTS

RESET MR

D0
D1
D2
D3
D4
D5
D6
D7

Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7

DAT A
OUTPUTS

TRUTH TABLE

INPUTS OUTPUT

RESET (MR) CLOCK CP DATA D

n

Q

LXXL
H ↑ HH
H ↑ LL
HLXQ

0

NOTE: H = High Voltage Level, L = Low VoltageLevel,X = Don’t Care,↑ = TransitionfromLow
to High Level, Q0= Level Before the Indicated Steady-State Input Conditions Were Established.

2

CD74HC273, CD74HCT273

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W) θJC (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . 125 N/A

CERDIP Package . . . . . . . . . . . . . . . . 105 44

SOIC Package. . . . . . . . . . . . . . . . . . . 120 N/A

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC273, CD74HCT273

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

∆I

CC

- - 4.5 to

- - 4.5 to

VIH or

V

VIH or

V

VCC to

GND

VCC or

GND

V

-2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

IL

CC

VCC (V)

5.5

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

MR 1.5

Data 0.4

CP 1.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

Maximum Clock Frequency
(Figure 1)

MR Pulse Width
(Figure 1)

f

MAX

t

CONDITIONS

W

V

CC

(V)

- 2 6 - - 5 - 4 - MHz

4.5 30 - - 25 - 20 - MHz
6 35 - - 29 - 23 - MHz

- 2 60 - - 75 - 90 - ns

4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC273, CD74HCT273

Prerequisite For Switching Specifications (Continued)

PARAMETER SYMBOL

Clock Pulse Width (Figure 1) t

Set-up Time Data to Clock
(Figure 5)

Hold Time, Data to Clock
(Figure 5)

Removal Time, MR to Clock t

HCT TYPES

Maximum Clock Frequency

f

(Figure 2)
MR Pulse Width

(Figure 2)
Clock Pulse Width (Figure 2) t
Set-up Time Data to Clock

(Figure 6)
Hold Time, Data to Clock

(Figure 6)
Removal Time, MR to Clock t

W

t

SU

t

H

REM

MAX

t

w

w

t

SU

t

H

REM

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

- 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

- 2 60 - - 75 - 70 - ns

4.5 12 - - 15 - 18 - ns
6 10 - - 13 - 15 - ns

-23--3-3-ns

4.5 3 - - 3 - 3 - ns
63--3-3-ns

- 2 50 - - 65 - 75 - ns

4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns

- 4.5 25 - - 20 - 16 - MHz

- 4.5 12 - - 15 - 18 - ns

- 4.5 20 - - 25 - 30 - ns

- 4.5 12 - - 15 - 18 - ns

- 4.5 3 - - 3 - 3 - ns

- 4.5 10 - - 13 - 15 - ns

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Clock to Output
(Figure 3)

Propagation Delay,
MR to Output
(Figure 3)

Output Transition Time
(Figure 3)

Input Capacitance C
Maximum Clock Frequency f

t

PLH

t

TLH

, t

PHLCL

t

PHL

, t

THLCL

I

MAX

, tf = 6ns

r

-55oC TO

TEST

25oC -40oC TO 85oC

125oC

CONDITIONS VCC (V)

= 50pF 2 - 150 190 225 ns

4.5 - 30 38 45 ns
6 - 26 30 38 ns

CL= 15pF 5 12 - - - ns
CL= 50pF 2 - 150 190 225 ns

4.5 - 30 38 45 ns
6 - 26 30 38 ns

= 50pF 2 - 75 95 110 ns

4.5 - 15 19 22 ns
6 - 13 16 19 ns

---1010 10pF

CL= 15pF 5 60 - - - MHz

UNITSTYP MAX MAX MAX

5

CD74HC273, CD74HCT273

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Power Dissipation

C

PD

CONDITIONS VCC (V)

- 5 25 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay,
Clock to Output (Figure 4)

Propagation Delay,

t

PLH

, t

PHLCL

t

PHL

= 50pF 4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
CL= 50pF 4.5 - 32 40 48 ns

MR to Output (Figure 4)
Output Transition Time t
Input Capacitance C
Maximum Clock Frequency f
Power Dissipation

TLH

, t

THLCL

IN

MAX

C

PD

= 50pF 4.5 - 15 19 22 ns

---1010 10pF

CL= 15pF 5 50 - - - MHz

- 5 25 - - - pF
Capacitance
(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per flip-flop.

6. PD=CPDV

CC

2

fi+ ∑ (CLV

2

+fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC= Supply

CC

Voltage.

25oC -40oC TO 85oC

-55oC TO
125oC

UNITSTYP MAX MAX MAX

Test Circuits and Waveforms

t

TLH

fC

50%

V

CC

GND

I

L

V

CC

GND

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

1.3V

I

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD74HC273, CD74HCT273

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

C
50pF

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

(Continued)

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

L

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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