Texas Instruments CD74HCT237E, CD74HCT137M96, CD74HCT137E, CD74HC237M96, CD74HC237M Datasheet

CD74HC137, CD74HCT137,

/
j

[ /Title
(CD74
HC137
,
CD74
HCT13
7,
CD74
HC237
,
CD74
HCT23

7)
Sub­ect

(High
Speed

Data sheet acquired from Harris Semiconductor
SCHS146

March 1998

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for CD74HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V
15pF, T

= 25oC (CD74HC237)

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30%, of V

IL

at VCC = 5V

CC

= 5V,

o

CD74HC237, CD74HCT237

High Speed CMOS Logic, 3-to-8 Line Decoder

Demultiplexer with Address Latches

C to 125oC

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Pinout

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

(PDIP, SOIC)

TOP VIEW

16

A
A
A

LE
OE
OE

Y

GND

1

0

2

1

3

3

4
5

1

6

0

7

7

8

V

CC

15

Y

0

14

Y

1

13

Y

2

12

Y

3

11

Y

4

10

Y

5

9

Y

6

OH

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1886.1

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

Description

The Harris CD74HC137, CD74HC237 and CD74HCT137,
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.

Both circuits have three binary selectinputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE) sig­nal to isolate the outputs from select-input changes. A “Low”
LE makes the output transparent to the input and the circuit
functions as a one-of-eight decoder. Two Output Enable
inputs (

OE1and OE0) are provided to simplify cascading
and to facilitate demultiplexing. The demultiplexing function
is accomplished by using the A

0,A1,A2

inputs to select the
desired output and using one of the other Output Enable
inputs as the data input while holding the other Output
Enable input in its active state. In the CD74HC137 and
CD74HCT137 the selected output is a “Low”; in the
CD74HC237 and CD74HCT237 the selected output is a
“High”.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC137E -55 to 125 16 Ld PDIP E16.3
CD74HCT137E -55 to 125 16 Ld PDIP E16.3
CD74HC237E -55 to 125 16 Ld PDIP E16.3
CD74HC237M -55 to 125 16 Ld SOIC M16.15
CD74HCT237E -55 to 125 16 Ld PDIP E16.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

NO.

2

CD74HC137, CD74HCT137, CD74HC237, CD74HCT237

Functional Diagram

HC/HCT HC/HCT

237 137

1

A

0

2

3-BIT

A

1

OE

OE

A

LE

LATCH

3

2

4

1

0

GND = 8

V

CC

1 OF 8

DECODER

5

6

= 16

CD74HC137, CD74HCT137 TRUTH TABLE

INPUTS OUTPUTS

LE OE

OE

0

A

1

A

2

A

1

0

Y

0

XXHXXXHHHHHHHH
XLXXXXHHHHHHHH
LHLLLLLHHHHHHH
LHLLLHHLHHHHHH
LHLLHLHHLHHHHH
LHLLHHHHHLHHHH
LHLHLLHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
LHLHHHHHHHHHHL
H H L X X X Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

15

14

13

12

11

10

9

7

Y

1

Y

Y

0

0

Y

Y

1

1

Y

Y

2

2

Y

Y

3

3

Y

Y

4

4

Y

Y

5

5

Y

Y

6

6

Y

Y

7

7

Y

Y

2

Y

3

Y

4

Y

5

Y

6

7

CD74HC237, CD74HCT237 TRUTH TABLE

INPUTS OUTPUTS

LE OE

OE

0

A

1

A

2

A

1

0

Y

0

Y

1

Y

Y

2

Y

3

Y

4

Y

5

Y

6

XXHXXXLLLLLLLL
XLXXXXLLLLLLLL
LHLLLLHLLLLLLL
LHLLLHLHLLLLLL
LHLLHLLLHLLLLL
LHLLHHLLLHLLLL
LHLHLLLLLLHLLL
LHLHLHLLLLLHLL
LHLHHLLLLLLLHL
LHLHHHLLLLLLLH
H H L X X X Depends upon the address previously applied while LE was at a logic low.

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

3

7