Texas Instruments CD74HCT193E, CD74HC193M96, CD74HC193M, CD74HC193E, CD74HC192E Datasheet
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1
Data sheet acquired from Harris Semiconductor
SCHS163
Features
• Synchronous Counting and Asynchronous
Loading
• Two Outputs for N-Bit Cascading
• Look-Ahead Carry for High-Speed Counting
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, NIH = 30% of V
CC
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at VOL, V
OH
Pinout
CD74HC192, CD74HC193, CD74HCT193
(PDIP, SOIC)
TOP VIEW
Description
The Harris CD74HC192, CD74HC193and CD74HCT193 are
asynchronously presettable BCD Decade and Binary
Up/Down synchronous counters, respectively.
Presetting thecounter to the number on the preset data inputs
(P0-P3) is accomplished by a LOW asynchronous parallel
load input (
PL). The counter is incremented on the low-to-high
transition of the Clock-Up input (and a high level on the ClockDown input) and decremented on the low to high transition of
the Clock-Down input (and a high level on the Clock-up input).
A high level on the MR input overrides any other input to clear
the counter to its zero state. The Terminal Count up (carry)
goes low half a clock period before the zero count is reached
and returns to a high level at the zero count. The Terminal
Count Down (borrow) in the count down mode likewise goes
low half a clock period before the maximum count (9 in the
192 and 15 in the 193) and returns to high at the maximum
count. Cascading is effected by connecting the carry and
borrow outputs of a less significant counter to the Clock-Up
and CLock-Down inputs, respectively, of the next most
significant counter.
If a decade counter is present to an illegal state or assumes
an illegal state when power is applied, it will return to the
normal sequence in one count as shown in state diagram.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
P1
Q1
Q0
CPD
CPU
Q2
GND
Q3
V
CC
MR
TCD
TCU
PL
P2
P3
P0
Ordering Information
PART NUMBER
TEMP.RANGE
(oC) PACKAGE
PKG.
NO.
CD74HC192E -55 to 125 16 Ld PDIP E16.3
CD74HC193E -55 to 125 16 Ld PDIP E16.3
CD74HCT193E -55 to 125 16 Ld PDIP E16.3
CD74HCT193M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or diefor this partnumber is availablewhich meets allelectrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
September 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
File Number 1674.1
CD74HC192, CD74HC193,
CD74HCT193
High Speed CMOS Logic
Presettable Synchronous 4-Bit Up/Down Counters
[ /Title
(CD74
HC192
,
CD74
HC193
,
CD74
HCT19
3)
/
Sub-
j
ect
(High
Speed
CMOS
Logic
Preset-
2
Functional Diagram
TRUTH TABLE
CLOCK UP
CLOCK
DOWN RESET
PARALLEL
LOAD FUNCTION
↑ H L H Count Up
H ↑ L H Count Down
X X H X Reset
X X L L Load Preset Inputs
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from
Low to High Level
ASYN.
MASTER
CLOCK UP
11
14
5
4
15 1 10 9
3
6
7
12
13
Q
0
Q
1
Q
2
Q
3
TERMINAL
P0 P1 P2 P3
LOAD
CLOCK DOWN
2
TERMINAL
COUNT UP
BCD (192)
BINARY (193)
OUTPUTS
BCD/BINARY
PRESET
ENABLE
PARALLEL
PL
RESET
COUNT DOWN
CD74HC192, CD74HC193, CD74HCT193
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
OH
VIH or
V
IL
-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
OL
VIH or
V
IL
0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
VCC or
GND
-6--±0.1 - ±1-±1 µA
Quiescent Device
Current
I
CC
VCC or
GND
0 6 - - 8 - 80 - 160 µA
CD74HC192, CD74HC193, CD74HCT193
4
HCT TYPES
High Level Input
Voltage
V
IH
- - 4.5 to
5.5
2-- 2 - 2 - V
Low Level Input
Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
High Level Output
Voltage
CMOS Loads
V
OH
VIH or
V
IL
- 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output
Voltage
TTL Loads
- 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output
Voltage
CMOS Loads
V
OL
VIH or
V
IL
- 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
I
I
VCC to
GND
- 5.5 - - ±0.1 - ±1-±1 µA
Quiescent Device
Current
I
CC
VCC or
GND
- 5.5 - - 8 - 80 - 160 µA
Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)
∆I
CC
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
NOTE:
4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT UNIT LOADS
P0-P3 0.4
MR 1.45
PL 0.85
CPU, CPD 1.45
NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.
CD74HC192, CD74HC193, CD74HCT193
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