Datasheet CD74HCT154M, CD74HCT154EN, CD74HCT154E, CD74HC154M96, CD74HC154M Datasheet (Texas Instruments)

CD74HC154,

/
j

[ /Title
(CD74
HC154
,
CD74
HCT15

4)
Sub­ect

(High
Speed
CMOS
Logic
4-to-16
Line
Decod
er/Dem

Data sheet acquired from Harris Semiconductor
SCHS152

September 1997

Features

• Two Enable Inputs to Facilitate Demultiplexing and
Cascading Functions

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT154

High Speed CMOS Logic

4-to-16 Line Decoder/Demultiplexer

Description

The Harris CD74HC154 and CD74HCT154 are 4-to-16 line
decoders/demultiplexers with two enable inputs, E1 and E2.
A High on either enable input forces the output into the High
state. The demultiplexing function is performed by using the
four input lines, A0 to A3, to select the output lines
Y15, and using one enable as the data input while holding
the other enable low.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC154E -55 to 125 24 Ld PDIP E24.6
CD74HCT154E -55 to 125 24 Ld PDIP E24.6
CD74HC154EN -55 to 125 24 Ld PDIP E24.3
CD74HC154EN -55 to 125 24 Ld PDIP E24.3
CD74HC154M -55 to 125 24 Ld SOIC M24.3
CD74HCT154M -55 to 125 24 Ld SOIC M24.3

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer or d ie for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

Y0 to

PKG.

NO.

Pinout

CD74HC154, CD74HCT154

(PDIP, SOIC)

TOP VIEW

1

Y0

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

8

Y7

9

Y8

10

Y9

11

Y10

12

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

24

V

CC

A0

23
22

A1

21

A2

20

A3

19

E2

18

E1

17

Y15

16

Y14

15

Y13

14

Y12

13

Y11

File Number 1657.1

Functional Diagram

CD74HC154, CD74HCT154

1

Y0

2

Y1

3

Y2

4

Y3

5

Y4

6

Y5

7

Y6

A0
A1
A2
A3

E1
E2

23
22
21
20

18
19

8

Y7

9

Y8

10

Y9

11

Y10

13

Y11

14

Y12

15

Y13

16

Y14

17

Y15

GND = 12

V

= 24

CC

TRUTH TABLE

INPUTS OUTPUTS

E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15

LLLLLLLHHHHHHHHHHHHHHH
LLLLLHHLHHHHHHHHHHHHHH
LLLLHLHHLHHHHHHHHHHHHH
LLLLHHHHHLHHHHHHHHHHHH
LLLHLLHHHHLHHHHHHHHHHH
LLLHLHHHHHHLHHHHHHHHHH
LLLHHLHHHHHHLHHHHHHHHH
LLLHHHHHHHHHHLHHHHHHHH
LLHLLLHHHHHHHHLHHHHHHH
LLLHLHHHHHHHHHHLHHHHHH
LLHLHLHHHHHHHHHHLHHHHH
LLHLHHHHHHHHHHHHHLHHHH
LLHHLLHHHHHHHHHHHHLHHH
LLHHLHHHHHHHHHHHHHHLHH
LLHHHLHHHHHHHHHHHHHHLH
LLHHHHHHHHHHHHHHHHHHHL

LHXXXXHHHHHHHHHHHHHHHH
HLXXXXHHHHHHHHHHHHHHHH
HHXXXXHHHHHHHHHHHHHHHH

NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

2

CD74HC154, CD74HCT154

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package (.300). . . . . . . . . . . . . . . . . . . . . . . . 75

PDIP Package (.600). . . . . . . . . . . . . . . . . . . . . . . . 60

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC154, CD74HCT154

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent

I

I

I

CC

∆I

CC

Device Current Per
Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1 µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

A0 - A3 1.4

E1, E2 1.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay (Figure 1) t

Address to Output 4.5 - - 35 - 44 - 53 ns

E1 to Output t

, tf = 6ns

r

CONDITIONS VCC(V)

PLH,tPHLCL

CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns

PLH,tPHLCL

CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns

-40oC TO

TEST

25oC

85oC -55oC TO 125oC

= 50pF 2 - - 175 - 220 - 265 ns

= 50pF 2 - - 175 - 220 - 265 ns

4.5 - - 35 - 44 - 53 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC154, CD74HCT154

Switching Specifications Input t

, tf = 6ns (Continued)

r

-40oC TO

PARAMETER SYMBOL

E2 to Output t

CONDITIONS VCC(V)

PLH,tPHLCL

TEST

25oC

= 50pF 2 - - 175 - 220 - 265 ns

85oC -55oC TO 125oC

4.5 - - 35 - 44 - 53 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 45 ns

Output Transition Time
(Figure 1)

t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns
Input Capacitance C
Power Dissipation Capacitance

IN

C

PD

- - - - 10 - 10 - 10 pF

-5-88-----pF

(Notes 4, 5)

HCT TYPES

Propagation Delay (Figure 2) t

PLH

, t

PHL

Address to Output CL= 50pF 4.5 - - 35 - 44 - 53 ns

CL=15pF 5 - 14 - - - - ns

E1 to Output t

PLH

, t

PHLCL

= 50pF 4.5 - - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns

E2 to Output t

PLH

, t

PHLCL

= 50pF 4.5 - 34 - 43 - 51 ns

CL=15pF 5 - 14 - - - - - ns
Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

IN

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5 84 - - - - - pF

(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = V

2

fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

INVERTING

OUTPUT

t

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

3V

GND

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