CD74HC154,
[ /Title
(CD74
HC154
,
CD74
HCT15
4)
Subect
(High
Speed
CMOS
Logic
4-to-16
Line
Decod
er/Dem
Data sheet acquired from Harris Semiconductor
SCHS152
September 1997
Features
• Two Enable Inputs to Facilitate Demultiplexing and
Cascading Functions
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
V
= 5V
CC
= 30%, NIH= 30%of VCCat
IL
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
≤ 1µA at VOL, V
l
o
C to 125oC
OH
CD74HCT154
High Speed CMOS Logic
4-to-16 Line Decoder/Demultiplexer
Description
The Harris CD74HC154 and CD74HCT154 are 4-to-16 line
decoders/demultiplexers with two enable inputs, E1 and E2.
A High on either enable input forces the output into the High
state. The demultiplexing function is performed by using the
four input lines, A0 to A3, to select the output lines
Y15, and using one enable as the data input while holding
the other enable low.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC154E -55 to 125 24 Ld PDIP E24.6
CD74HCT154E -55 to 125 24 Ld PDIP E24.6
CD74HC154EN -55 to 125 24 Ld PDIP E24.3
CD74HC154EN -55 to 125 24 Ld PDIP E24.3
CD74HC154M -55 to 125 24 Ld SOIC M24.3
CD74HCT154M -55 to 125 24 Ld SOIC M24.3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or d ie for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
Y0 to
PKG.
NO.
Pinout
CD74HC154, CD74HCT154
(PDIP, SOIC)
TOP VIEW
1
Y0
2
Y1
3
Y2
4
Y3
5
Y4
6
Y5
7
Y6
8
Y7
9
Y8
10
Y9
11
Y10
12
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
24
V
CC
A0
23
22
A1
21
A2
20
A3
19
E2
18
E1
17
Y15
16
Y14
15
Y13
14
Y12
13
Y11
File Number 1657.1
Functional Diagram
CD74HC154, CD74HCT154
1
Y0
2
Y1
3
Y2
4
Y3
5
Y4
6
Y5
7
Y6
A0
A1
A2
A3
E1
E2
23
22
21
20
18
19
8
Y7
9
Y8
10
Y9
11
Y10
13
Y11
14
Y12
15
Y13
16
Y14
17
Y15
GND = 12
V
= 24
CC
TRUTH TABLE
INPUTS OUTPUTS
E1 E2 A3 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15
LLLLLLLHHHHHHHHHHHHHHH
LLLLLHHLHHHHHHHHHHHHHH
LLLLHLHHLHHHHHHHHHHHHH
LLLLHHHHHLHHHHHHHHHHHH
LLLHLLHHHHLHHHHHHHHHHH
LLLHLHHHHHHLHHHHHHHHHH
LLLHHLHHHHHHLHHHHHHHHH
LLLHHHHHHHHHHLHHHHHHHH
LLHLLLHHHHHHHHLHHHHHHH
LLLHLHHHHHHHHHHLHHHHHH
LLHLHLHHHHHHHHHHLHHHHH
LLHLHHHHHHHHHHHHHLHHHH
LLHHLLHHHHHHHHHHHHLHHH
LLHHLHHHHHHHHHHHHHHLHH
LLHHHLHHHHHHHHHHHHHHLH
LLHHHHHHHHHHHHHHHHHHHL
LHXXXXHHHHHHHHHHHHHHHH
HLXXXXHHHHHHHHHHHHHHHH
HHXXXXHHHHHHHHHHHHHHHH
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2