TEXAS INSTRUMENTS CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Technical data

CD54HC14, CD74HC14,

[ ( C C C / ( S C L H I

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CD54HCT14, CD74HCT14

Data sheet acquired from Harris Semiconductor SCHS129C

January 1998 - Revised September 2003

High-Speed CMOS Logic

Hex Inverting Schmitt Trigger

/Title CD74H

14, D74H

T14) Subject High

peed

MOS

ogic

ex nvert-

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

- CMOS Input Compatibility, I

VIL= 0.8V (Max), VIH = 2V (Min)

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

Description

The ’HC14 and ’HCT14 each contain six inverting Schmitt triggers in one package.

Ordering Information

TEMP. RANGE

PART NUMBER

CD54HC14F3A -55 to 125 14 Ld CERDIP CD54HCT14F3A -55 to 125 14 Ld CERDIP CD74HC14E -55 to 125 14 Ld PDIP CD74HC14M -55 to 125 14 Ld SOIC CD74HC14MT -55 to 125 14 Ld SOIC

CC

CD74HC14M96 -55 to 125 14 Ld SOIC CD74HCT14E -55 to 125 14 Ld PDIP CD74HCT14M -55 to 125 14 Ld SOIC CD74HCT14MT -55 to 125 14 Ld SOIC CD74HCT14M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entirepart number. The sufﬁx96 denotes tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

(oC) PACKAGE

Pinout

CD54HC14, CD54HCT14

(CERDIP)

CD74HC14, CD74HCT14

(PDIP, SOIC)

TOP VIEW

1A

1 2

1Y 2A

3

2Y

4

3A

5

3Y

6

GND

7

V

14

CC

6A

13

6Y

12

5A

11

5Y

10

4A

9

4Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

1

Functional Diagram

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CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

1A

2A

3A

4A

5A

1

3

5

9

11

2

1Y

4

2Y

6

3Y

8

4Y

10

5Y

13

6A

12

6Y GND = 7 V

= 14

CC

INPUT (A) OUTPUT (Y)

H= High Level L= Low Level

LH

HL

TRUTH TABLE

Logic Diagram

nA nY

V

O

V

CC

V

I

GND

V

CC

V

O

GND

V

H

VH = VT+ - VT-

V

I

VT-VT+

+V

V

T

-

T

V

H

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SETUP

2

CD54HC14, CD74HC14, CD54HCT, CD74HCT14

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Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

For -0.5V < VO < VCC +0.5V . . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time, tr, t

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

DC Electrical Speciﬁcations

1. The package thermal impedance is calculated in accordance with JESD 51-7.

PARAMETER SYMBOL

HC TYPES

Input Switch Points V

IK

OK

O

CC

f

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

CC

+ - - 2 0.7 1.5 0.7 1.5 0.7 1.5 V

T

V

- - - 2 0.3 1.0 0.3 1.0 0.3 1.0 V

T

V

H

- - 2 0.2 1.0 0.2 1.0 0.2 1.0 V

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

V

OH

VT- or

VT+

-0.02 2 1.9 - 1.9 - 1.9 - V

-0.02 4.5 4.4 - 4.4 - 4.4 - V

-0.02 6 5.9 - 5.9 - 5.9 - V

--------V

-4 4.5 3.98 - 3.84 - 3.7 - V

-5.2 6 5.48 - 5.34 - 5.2 - V

Thermal Resistance (Typical, Note 1) θJA (oC/W)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

o

C -40oC TO 85oC -55oC TO 125oC

25

(V)

4.5 1.7 3.15 1.7 3.15 1.7 3.15 V 6 2.1 4.2 2.1 4.2 2.1 4.2 V

4.5 0.9 2.2 0.9 2.2 0.9 2.2 V 6 1.2 3.0 1.2 3.0 1.2 3.0 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V 6 0.6 1.6 0.6 1.6 0.6 1.6 V

UNITSV

3

CD54HC14, CD74HC14, CD54HCT14, CD74HCT14

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DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

LowLevelOutputVoltage CMOS Loads

V

OL

LowLevel Output Voltage TTL Loads

Input Leakage Current I

I

Quiescent Device Current

HCT TYPES

Input Switch Points VT+ - - 4.5 1.2 1.9 1.2 1.9 1.2 1.9 V

I

CC

V

- 4.5 0.5 1.2 0.5 1.2 0.5 1.2 V

T

V

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

LowLevelOutputVoltage CMOS Loads

LowLevel Output Voltage TTL Loads

Input Leakage Current I

H

V

OH

V

OL

I

Quiescent Device Current

Additional Quiescent Device Current Per Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (V

HCT Input Loading Table

I

CC

∆I

CC

(Note 2)

TEST

CONDITIONS

V

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VIH or

V

VCC or

GND

VCC or

GND

VIH or

V

VIH or

V

CC

and

GND

VCC or

GND

V

CC

- 2.1

0.02 2 - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - 0.1 - 0.1 - 0.1 V

0.02 6 - 0.1 - 0.1 - 0.1 V

--------V

4 4.5 - 0.26 - 0.33 - 0.4 V

5.2 6 - 0.26 - 0.33 - 0.4 V

-6-±0.1 - ±1-±1 µA

06-2-20-40µA

-0.02 4.5 4.4 - 4.4 - 4.4 - V

IL

-4 4.5 3.98 - 3.84 - 3.7 - V

0.02 4.5 - 0.1 - 0.1 - 0.1 V

IL

4 4.5 - 0.26 - 0.33 - 0.4 V

- 5.5 - ±0.1 - ±1-±1 µA

0 5.5 - 2 - 20 - 40 µA

- 4.5 to

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

(V)

CC

5.5 1.4 2.1 1.4 2.1 1.4 2.1 V

5.5 0.6 1.4 0.6 1.4 0.6 1.4 V

4.5 0.4 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 1.5 0.4 1.5 0.4 1.5 V

5.5

o

C -40oC TO 85oC -55oC TO 125oC

25

- 360 - 450 - 490 µA

UNITSV

INPUT UNIT LOADS

nA 0.6

NOTE: Unit Load is ∆I tions table, e.g., 360µA max at 25oC.

limit speciﬁed in DC Electrical Speciﬁca-

CC

4

Switching Speciﬁcations Input t

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HC TYPES

Propagation Delay, A to Y

PARAMETER SYMBOL

Output Transition Times t

Input Capacitance C Power Dissipation Capacitance

(Notes 3, 4)

HCT TYPES

Propagation Delay, A to Y

Output Transition Times t Input Capacitance C Power Dissipation Capacitance

(Notes 3, 4)

NOTES:

3. C

4. PD = V

is used to determine the dynamic power consumption, per inverter.

PD

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

t

PLH

TLH

t

PLH

TLH

, tf = 6ns

r

, t

PHLCL

, t

THLCL

I

C

PD

, t

PHLCL

, t

THLCL

I

C

PD

o

C -40oC TO 85oC -55oC TO 125oC

TEST

CONDITIONS

= 50pF 2 - - 135 - 170 - 205 ns

C

= 50pF 4.5 - - 27 - 34 - 41 ns

L

C

= 15pF 5 - 11 - ----ns

L

C

= 50pF 6 - - 23 - 29 - 35 ns

L

= 50pF 2 - - 75 - 95 18 110 ns

- - - - 10 - 10 - 10 pF

- 5-20-----pF

= 50pF 4.5 - - 38 - 48 - 57 ns

C

= 15pF 5 - 16 - ----ns

L

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-20-----pF

V

CC

(V)

4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns

25

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

INVERTING

OUTPUT

FIGURE 4. HCTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

90% 50% 10%

t

THL

t

PHL

t

10%

PLH

90%

50%

t

TLH

V

CC

GND

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

t

PHL

2.7V

1.3V

0.3V

INPUT

t

THL

INVERTING

OUTPUT

FIGURE 5. HCTTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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MECHANICAL

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MPDI002C – JANUARY 1995 – REVISED DECEMBER 20002

N (R-PDIP-T**) PLASTIC DUAL-IN-LINE PACKAGE

16 PINS SHOWN

PINS **

DIM

A

16

9

0.260 (6,60)

0.240 (6,10)

C

A MAX

A MIN

MS-100

VARIATION

0.775

(19,69)

0.745

(18,92)

AA

1

0.070 (1,78)

0.045 (1,14)

8

D

0.045 (1,14)

0.030 (0,76)

D

0.020 (0,51) MIN

0.200 (5,08) MAX Seating Plane

0.325 (8,26)

0.300 (7,62)

0.125 (3,18) MIN

14

16

0.775

(19,69)

0.745

(18,92)

BB AC AD

18

0.920

(23,37)

0.850

(21,59)

0.015 (0,38)

Gauge Plane

0.010 (0,25) NOM

20

1.060

(26,92)

0.940

(23,88)

0.021 (0,53)

0.015 (0,38)

0.010 (0,25)

0.100 (2,54)

M

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice.

C. Falls within JEDEC MS-001, except 18 and 20 pin minimum body lrngth (Dim A). D. The 20 pin end lead shoulder width is a vendor option, either half or full width.

14/18 PIN ONLY 20 pin vendor option

0.430 (10,92) MAX

D

4040049/E 12/2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

MECHANICAL DATA

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MSOI002B – JANUARY 1995 – REVISED SEPTEMBER 2001

D (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

8 PINS SHOWN

0.020 (0,51)

0.014 (0,35)

8 5

0.010 (0,25)0.050 (1,27)

0.157 (4,00)

0.150 (3,81)

0.244 (6,20)

0.228 (5,80)

0.008 (0,20) NOM

1 4

A

0°– 8°

0.069 (1,75) MAX

0.010 (0,25)

0.004 (0,10)

Seating Plane

0.004 (0,10)

Gage Plane

0.010 (0,25)

0.044 (1,12)

0.016 (0,40)

PINS **

DIM

A MAX

A MIN

NOTES: A. All linear dimensions are in inches (millimeters).

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion, not to exceed 0.006 (0,15). D. Falls within JEDEC MS-012

8

0.197 (5,00)

0.189 (4,80)

14

0.344 (8,75)

0.337 (8,55)

16

0.394

(10,00)

0.386

(9,80)

4040047/E 09/01

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

1

TEXAS INSTRUMENTS CD54HC14, CD74HC14, CD54HCT14, CD74HCT14 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual