Texas Instruments CD74HCT132E, CD74HCT132M96, CD74HCT132M, CD74HC132M96, CD74HC132M Datasheet

CD74HC132,

/
j

[ /Title
(CD74
HC132
,
CD74
HCT13

2)
Sub­ect

(High
Speed
CMOS
Logic
Quad
2-Input
NAND
Schmit

Data sheet acquired from Harris Semiconductor
SCHS145

August 1997

Features

• Unlimited Input Rise and Fall Times

• Exceptionally High Noise Immunity

• Typical Propagation Delay: 10ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 37%, NIH = 51% of V

IL

CC

= 5V,

o

Pinout

Quad 2-Input NAND Schmitt Trigger

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

IL

- CMOS Input Compatibility, I

• Related Literature

- CD54HC132F3A and CD54HCT132F3A Military
Data Sheet, Document Number 3778

C to 125oC

CD74HC132, CD74HCT132

Description

The Harris CD74HC132, CD74HCT132 each contain four
2-input NAND Schmitt Triggers in one package. This logic
device utilizes silicon gate CMOS technology to achieve
operating speeds similar to LSTTL gates with the low power
consumption of standard CMOS integrated circuits. All
devices have the ability to drive 10 LSTTL loads. The 74HCT

CC

(PDIP, SOIC)

TOP VIEW

CD74HCT132

High Speed CMOS Logic

= 0.8V (Max), VIH = 2V (Min)

l

≤ 1µA at VOL, V

OH

1A
1B

1Y
2A
2B

2Y

GND

1
2
3
4
5
6
7

14

V

CC

4B

13
12

4A
4Y

11

3B

10

3A

9

3Y

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1649.1

Functional Diagram

CD74HC132, CD74HCT132

1A

1B

1Y

2A

2B

2Y

GND

1

2

3

4

5

6

7

14

V

CC

13

4B

12

4A

11

4Y

10

3B

9

3A

8

3Y

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH
LHH
HLH

Logic Symbol

HHL

NOTE: H = High Voltage Level, L = Low Voltage Level

nA

nY

nB

2

CD74HC132, CD74HCT132

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100ms (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

Input Switch Points
(Note 6)

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

VT+ - - 2 0.7 - 1.5 0.7 1.5 0.7 1.5 V

VT- - - 2 0.3 - 1 0.3 1 0.3 1 V

V

H

V

OH

TEST

CONDITIONS

VT+ or

VT-

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

4.5 1.7 - 3.15 1.7 3.15 1.7 3.15 V
6 2.1 - 4.2 2.1 4.2 2.1 4.2 V

4.5 0.9 - 2.2 0.9 2.2 0.9 2.2 V
6 1.2 - 3 1.2 3 1.2 3 V
2 0.2 - 1 0.2 1 0.2 1 V

4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V
6 0.6 - 1.6 0.6 1.6 0.6 1.6 V

-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC132, CD74HCT132

DC Electrical Specifications (Continued)

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

Low Level Output
Voltage
CMOS Loads

V

OL

VT+ or

VT-

VCC (V)

0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

I

I

CC

VCC or

I

GND

VCC or

GND

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

-6--±0.1 - ±1-±1 µA

0 6 - - 2 - 20 - 40 µA

HCT TYPES

Input Switch Points
(Note 6)

VT+ - - 4.5 1.2 - 1.9 1.2 1.9 1.2 1.9 V

5.5 1.4 - 2.1 1.4 2.1 1.4 2.1 V

VT- - - 4.5 0.5 - 1.2 0.5 1.2 0.5 1.2 V

5.5 0.6 - 1.4 0.6 1.4 0.6 1.4 V

V

H

- - 4.5 0.4 - 1.4 0.4 1.4 0.4 1.4 V

5.5 0.4 - 1.5 0.4 1.5 0.4 1.5 V

High Level Output
Voltage

VT+

-

or

- 4.5 4.4 - - 4.4 - 4.4 - V

VT-

CMOS Loads
High Level Output

- 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VT+

-4 4.5 - - 0.1 - 0.1 - 0.1 V

or

VT-

0.02 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

4 5.5 - - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

VCC or

0 5.5 - - 2 - 20 - 40 µA

GND

∆I

CC

V

CC

- 2.1

- 4.5 to

5.5

- 100 360 - 450 - 490 µA

Input Pin: 1 Unit Load
(Note 4)

NOTES:

4. For dual-supply systems theorectical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

5. Die for this part number is available which meets all electrical specifications.

6. Hysteresis definition, characteristic and test setup see Test Circuits and Waveforms:

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

4

CD74HC132, CD74HCT132

HCT Input Loading Table

INPUT UNIT LOADS

nA, nB 0.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g. 360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

, tf = 6ns

r

TEST

CONDITIONS

V

CC

(V)

HC TYPES

Propagation Delay
A, B to Y (Figure 1)

t

PLH

, t

PHLCL

= 50pF 2 - - 125 - 156 - 188 ns

4.5 - - 25 - 31 - 38 ns
6 - - 21 - 27 - 32 ns

Propagation Delay

t

TLH

, t

THLCL

= 15pF 5 - 10 - ----pF

A, B to Y
Transition Times (Figure 1) t

TLH

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Input Capacitance C
Power Dissipation Capacitance

C

I

PD

- - - - 10 - 10 - 10 pF

- 5-30-----pF

(Notes 7, 8)

HCT TYPES

Propagation Delay

t

PHL

, t

PHLCL

= 50pF 4.5 - - 33 - 41 - 50 ns
A, B to Y
(Figure 2)

Propagation Delay

t

PLH

, t

PHLCL

= 15pF 5 - 13 - ----pF
A, B to Y

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-30-----pF

(Notes 7, 8)

NOTES:

7. CPD is used to determine the dynamic power consumption, per gate.

8. PD = V

2

fi (CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

5

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

CD74HC132, CD74HCT132

tr = 6ns

V

CC

GND

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

V

-

V

T

V

CC

GND

V

CC

V

GND

V

O

+

V

T

V

l

O

t

THL

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

H

+

-

- V

T

T

V

l

-

V

T

V

H

V

CC

V

V

l

O

V

VH= V

+
T

t

TLH

FIGURE 3. HYSTERESIS DEFINITION, CHARACTERISTIC, AND TEST SET-UP

6

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