Texas Instruments CD74HCT73M, CD74HCT73E, CD74HC73M96, CD74HC73M, CD74HC73E Datasheet

CD74HC73,

/
j

[ /Title
(CD74
HC73,
CD74
HCT73
)

Sub-

ect
(Dual
J-K
Flip­Flop

Data sheet acquired from Harris Semiconductor
SCHS134

February 1998

Features

• Hysteresis on Clock Inputs for Improved Noise
Immunity and Increased Input Rise and Fall Times

• Asynchronous Reset

• Complementary Outputs

• Buffered Inputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), VIH = 2V (Min)

V

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

C to 125oC

CC

OH

CD74HCT73

Dual J-K Flip-Flop with Reset

Negative-Edge Trigger

Description

The Harris CD74HC73 and CD74HCT73 utilize silicon gate
CMOS technology to achieve operating speeds equivalent to
LSTTL parts. They exhibit the low power consumption of
standard CMOS integrated circuits, together with the ability
to drive 10 LSTTL loads.

These flip-flops have independent J, K, Reset and Clock
inputs and Q and
negative-going transition of the clock pulse. Reset is
accomplished asynchronously by a low level input. This
device is functionally identical to the HC/HCT107 but differs
in terminal assignment and in some parametric limits.

The 74HCT logic family is functionally as well as pin
compatible with the standard 74LS logic family.

Ordering Information

PART NUMBER

CD74HC73E -55 to 125 14 Ld PDIP E14.3
CD74HCT73E -55 to 125 14 Ld PDIP E14.3
CD74HC73M -55 to 125 14 Ld SOIC M14.15

NOTES:

6. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

7. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

Q outputs. They change state on the

TEMP. RANGE

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC73, CD74HCT73

(PDIP, SOIC)

TOP VIEW

1CP

1

1R

2
3

1K

V

4

CC

2CP

5

2R

6

2J

7

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

14

1J
1Q

13
12

1Q
GND

11

2K

10

2Q

9

2Q

8

1

File Number 1721.1

Functional Diagram

CD74HC73, CD74HCT73

R CP J K Q Q

LXXXLH

H
H

H
H
H H X X No Change

NOTE:
H =High Level (Steady State)
L =Low Level (Steady State)
X = Irrelevant

↓

= High-to-Low Transition

1K

1CP

1

2K

2CP

2R

14

1J

3

1

2

R

7

2J

10

5

6

FF 1

FF 2

12

1Q

13

Q

1

9

2Q

8

2

Q

GND = 11

= 4

V

CC

TRUTH TABLE

INPUTS OUTPUTS

↓
↓
↓
↓

L L No Change

HLHL

LHLH

H H Toggle

Logic Diagram

CP

14 (7)

J

3(10)

K

1 (5)

nA

2 (6)

R

J
K
CL
CL

R

12 (9)

Q

13 (8)

Q

2

CD74HC73, CD74HCT73

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

8. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Hermetic P ac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC73, CD74HCT73

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

I

CC

VCC or

GND

VCC (V)

0 6 - - 4 - 40 - 80 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

- 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-0.02 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage CMOS Loads

Low Level Output

V

OL

VIH or

V

IL

-4 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

I

I

V

CC

4 5.5 - ±0.1 - ±1-±1 µA

and

GND

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

CC

VCC or

0 5.5 - - 4 - 40 - 80 µA

GND

∆I

CC

V

CC

- 2.1

- 4.5 to

5.5

Input Pin: 1 Unit Load

NOTE:

9. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 0.3

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

CP Pulse Width t

R Pulse Width t

CONDITIONS

-CL= 50pF 2 80 - - 100 - 120 - ns

w

-CL= 50pF 2 80 - - 100 - 120 - ns

w

HC TYPES HCT TYPES

Input Level V

V

S

50% V

CC

CC

3V

1.3V

NOTE: Transition times and propagation delay times.

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

4

CD74HC73, CD74HCT73

Prerequisite For Switching Specifications (Continued)

PARAMETER SYMBOL

Setup Time, J, K to CP t

Hold Time, J, K to CP t

Removal Time t

CP Frequency f

HCT TYPES

CP Pulse Width t
R Pulse Width t
Setup Time, J, K to CP t
Hold Time, J, K to CP t
Removal Time t
CP Frequency f

SU

H

REM

MAX

w
w

SU

H
REM
MAX

TEST

CONDITIONS

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CL= 50pF 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

CL= 50pF 2 3 - - 3 - 3 - ns

4.5 3 - - 3 - 3 - ns
63--3-3-ns

-CL= 50pF 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

CL= 50pF 2 6 - - 5 - 4 - MHz

4.5 30 - - 25 - 20 - MHz

CL= 15pF 5 - 60 - ----MHz
CL= 50pF 6 35 - - 29 - 23 - MHz

CL= 50pF 4.5 16 - - 20 - 24 - ns
CL = 50pF 4.5 18 - - 23 - 27 - ns
CL = 50pF 4.5 16 - - 20 - 24 - ns
CL = 50pF 4.5 3 - - 3 - 3 - ns
CL = 50pF 4.5 12 - - 15 - 18 - ns
CL = 50pF 4.5 30 - - 25 - 20 - MHz
CL = 15pF 5 - 60 - ----MHz

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
CP to Q

Propagation Delay,
CP to Q

Propagation Delay,
R to Q, Q

Output Transition Time t

t

PLH

t

PLH

t

PLH

TLH

, tf = 6ns

r

25oC -40oC TO 85oC -55oC TO 125oC

, t

PHLCL

TEST

CONDITIONS

V

CC

(V)

= 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns

CL = 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 28 - 34 - 41 ns

, t

PHLCL

= 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns

CL= 15pF 5 - 13 - ----ns
CL= 50pF 6 - - 28 - 34 - 41 ns

, t

PHLCL

= 50pF 2 - - 145 - 180 - 220 ns

4.5 - - 29 - 36 - 44 ns

CL= 15pF 5 - 12 - ----ns
CL= 50pF 6 - - 25 - 31 - 38 ns

, t

THLCL

= 50pF 2 - - 75 - 95 18 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC73, CD74HCT73

Switching Specifications Input t

PARAMETER SYMBOL

Input Capacitance C
Power Dissipation Capacitance

, tf = 6ns (Continued)

r

TEST

CONDITIONS

I

C

PD

- - - - 10 - 10 - 10 pF

- 5-28-----pF

V

CC

(V)

(Notes 5, 6)

HCT TYPES

Propagation Delay,

t

PLH

, t

PHLCL

= 50pF 4.5 - - 38 - 48 - 57 ns

CP to Q
Propagation Delay,

t

PLH

, t

CL = 50pF 4.5 - - 36 - 45 - 54 ns

PHL

CP to Q
Propagation Delay,

t

PLH

, t

CL = 50pF 4.5 - - 34 - 43 - 51 ns

PHL

R to Q, Q
Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance

TLH

, t

I

C

PD

THLCL

= 50pF 4.5 - - 15 - 19 - 22 ns

- - - - 10 - 10 - 10 pF

- 5-28-----pF

(Notes 5, 6)

NOTES:

10. CPD is used to determine the dynamic power consumption, per flip-flop.

11. PD=CPDV

CC

2

fi+ Σ CLV

2

fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, VCC= supply voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

t

TLH

f

CL

50%

V

CC

GND

I

V

CC

GND

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

1.3V

I

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

t

fCL

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 3. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 4. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 5. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6

CD74HC73, CD74HCT73

Test Circuits and Waveforms

90%

t

PLH

IC

t

TLH

tfC

L

50%

C
50pF

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

trC

L

90%

10%

t

H(H)

50%

(Continued)

t

H(L)

t

SU(L)

t

THL

90%

50%

10%
t

PHL

L

V

CC

GND

V

CC

50%
GND

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

trC

90%

t

PLH

IC

1.3V

t

TLH

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

t

THL

90%

1.3V
10%

t

PHL

C

L

50pF

3V

GND

3V

GND

GND

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

1.3V

FIGURE 6. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

FIGURE 7. HCT SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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