Texas Instruments CD74HCT688M96, CD74HCT688M, CD74HCT688E, CD74HC688PWR, CD74HC688M96 Datasheet

CD74HC688,

/
j

[ /Title
(CD74
HC688
,
CD74
HCT68

8)
Sub­ect

(High
Speed
CMOS

Data sheet acquired from Harris Semiconductor
SCHS196

September 1997

Features

• Cascadable

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

= 30%, NIH= 30%of VCCat

IL

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT688

High Speed CMOS Logic

8-Bit Magnitude Comparator

Description

The Harris CD74HC688 and CD74HCT688 are 8-bit
magnitude comparators designed for use in computer and
logic applications that require the comparison of two 8-bit
binary words. When the compared words are equal the
output (Y) is low and can be used as the enabling input for
the next device in a cascaded application.

Ordering Information

PKG.

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC688E -55 to 125 20 Ld PDIP E20.3
CD74HCT688E -55 to 125 20 Ld PDIP E20.3
CD74HC688M -55 to 125 20 Ld SOIC M20.3
CD74HCT688M -55 to 125 20 Ld SOIC M20.3
CD54HC688 -55 to 125 Wafer

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

NO.

Pinout

CD74HC688, CD74HCT688

(PDIP, SOIC)

TOP VIEW

1

E

A0

2

B0

3

A1

4

B1

5

A2

6

B2

7
8

A3

9

B3

GND

10

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

V

20

CC

Y

19

B7

18

A7

17

B6

16

A6

15

B5

14

A5

13
12

B4
A4

11

File Number 1646.1

Functional Diagram

CD74HC688, CD74HCT688

2

A0

4

A1

6

A2

8

A3

11

A4

13

A5

15

A6

17

A7
B0
B1
B2
B3
B4
B5
B6
B7

3
5
7

9
12
14
16
18

Y

19

E

1

TRUTH TABLE

INPUTS OUPUTS

A, B EY

A = B L L
A ≠ BL H

XH H

NOTES: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

2

Logic Diagram

A0 B0 A1 B1 A2 B2 A3 B3 A4 B4 A5 B5 A6 B6 A7 B7

2 3 4 5 6 7 8 9 11 12 13 14 15 16 17 18

CD74HC688, CD74HCT688

E

1

10

20

GND

V

CC

19

Y

3

CD74HC688, CD74HCT688

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

4

CD74HC688, CD74HCT688

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

(Note)

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

Enable 0.7

Data Inputs 0.35

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay (Figure 1) t

An to Output 4.5 - - 34 - 42 - 51 ns

Bn to Output t

PLH,

t

PHL

PLH,

t

PHL

, tf = 6ns

r

o

C -40oC TO 85oC -55oC TO 125oC

TEST

CONDITIONS

V

CC

(V)

25

CL= 50pF 2 - - 170 - 210 - 255 ns

C

=15pF 5 - 14 - - - - - ns

L

= 50pF 6 - - 29 - 36 - 43 ns

C

L

CL= 50pF 2 - - 170 - 210 - 255 ns

4.5 - - 34 - 42 - 51 ns

C

=15pF 5 - 14 - - - - - ns

L

C

= 50pF 6 - - 29 - 36 - 43 ns

L

UNITSMIN TYP MAX MIN MAX MIN MAX

5

CD74HC688, CD74HCT688

Switching Specifications Input t

PARAMETER SYMBOL

E to Output t

Output Transition Time
(Figure 1)

Input Capacitance C
Power Dissipation Capacitance

(Notes 4, 5)

HCT TYPES

Propagation Delay (Figure 1) t

An to Output C
Bn to Output t

E to Output t

Output Transition Time
(Figure 1)

Input Capacitance C
Power Dissipation Capacitance

(Notes 4, 5)

NOTES:

4. C

is used to determine the dynamic power consumption, per gate.

PD

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

PLH,

t

PHL

t

TLH,tTHLCL

C

PD

PLH,

t

PHL

PLH,

t

PHL

PLH,

t

PHL

t

TLH,tTHLCL

C

PD

, tf = 6ns (Continued)

r

o

C -40oC TO 85oC -55oC TO 125oC

TEST

CONDITIONS

V

CC

(V)

25

CL= 50pF 2 - - 120 - 150 - 180 ns

4.5 - - 24 - 30 - 36 ns

C

=15pF 5 - 9 - - - - - ns

L

C

= 50pF 6 - - 20 - 26 - 30 ns

L

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

CL= 50pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 22 - - - - - pF

CL= 50pF 4.5 - - 34 - 42 - 51 ns

=15pF 5 - 14 - - - - - ns

L

CL= 50pF 4.5 - - 34 - 42 - 51 ns
C

=15pF 5 - 14 - - - - - ns

L

CL= 50pF 4.5 - - 24 - 30 - 36 ns
C

=15pF 5 - 9 - - - - - ns

L

= 50pF 4.5 - - 15 - 19 - 22 ns

CL= 50pF - - - 10 - 10 - 10 pF

IN

CL=15pF 5 - 22 - - - - - pF

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuit and Waveform

tr = 6ns

ANY INPUT

A OR B

OUTPUT Y

FIGURE 1. PROPAGATION DELAY AMD TRANSITION TIMES

t

PLH

t

TLH

tf = 6ns

INPUT LEVEL

90%
V

S

10%

t

PHL

t

THL

GND

V

S

6

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