Texas Instruments CD74HCT640M, CD74HCT640E, CD74HC640M, CD74HC640E, CD54HCT640F3A Datasheet

CD74HC640,

/
j

[ /Title
(CD74
HC640
,
CD74
HCT64

0)
Sub­ect

(High
Speed
CMOS

Data sheet acquired from Harris Semiconductor
SCHS192

January 1998

Features

• Buffered Inputs

• Three-State Outputs

• Applications in Multiple-Data-Bus Architecture

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

o

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

Pinout

CD74HC640, CD74HCT640

CD74HCT640

High Speed CMOS Logic

Octal Three-State Bus Transceiver, Inverting

(PDIP, SOIC)

TOP VIEW

C to 125oC

CC

OH

1

DIR

A0

2

A1

3

A2

4

A3

5

A4

6

A5

7
8

A6

9

A7

GND

10

Description

The Harris CD74HC640 and CD74HCT640 silicon-gate
CMOS three-state bidirectional inverting and non-inverting
buffers are intended for two-way asynchronous
communication between data buses. They have high drive
current outputs which enable high-speed operation when
driving large bus capacitances. These circuits possess the
low power dissipation of CMOS circuits, and have speeds
comparable to low power Sckottky TTL circuits. They can
drive 15 LSTTL loads. The CD74HC640 and CD74HCT640
are inverting buffers.

V

20

CC

OE

19

B0

18

B1

17

B2

16

B3

15

B4

14

B5

13
12

B6
B7

11

Functional Diagram

A0

A1

THRU

A6

A7

OE

DIR

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

OUTPUT ENABLE AND

DIRECTION-SELECT LOGIC

1

B0

B1

THRU

B6

B7

VCC = 20

GND = 10

File Number 1677.1

CD74HC640, CD74HCT640CD74HC640, CD74HCT640

TRUTH TABLE

CONTROL INPUTS DATA PORT STATUS
OE DIR A

LLOI
HHZZ
HLZZ
LHIO

To prevent excess currents in the High-Z modes all I/O terminals
should be terminated with 1kΩ to 1MΩ resistors.
H = High Level
L = Low Level
I = Input
O = Output (Inversion of Input Level)
Z = High Impedance

n

B

n

2

CD74HC640, CD74HCT640CD74HC640, CD74HCT640

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

7. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

3

CD74HC640, CD74HCT640CD74HC640, CD74HCT640

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device

I

CC

Current
Three-State Leakage

Current

I

OZ

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

Additional Quiescent
Device Current Per

I

I

I

CC

I

OZ

∆I

CC

Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC or

0 6 - - 8 - 80 - 160 µA

GND

VILor VIHVO =

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

6 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

VILor VIHVO =

VCC or

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

25

(V)

6--±0.5 - ±5-±10 µA

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

5.5 - - ±0.5 - ±5-±10 µA

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

DIR 0.9

OE, A 1.5

B 1.5

NOTE: UnitLoad is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

4

CD74HC640, CD74HCT640CD74HC640, CD74HCT640

Switching Specifications C

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

A to

B

B to A

Output High-Z
To High Level,
To Low Level

Output High Level
Output Low Level to High Z

Output Transition Time t

Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

(Notes 4, 5)

HCT TYPES

Propagation Delay

A to

B

B to A

Output High-Z
To High Level,
To Low Level

Output High Level
Output Low Level to High Z

Output Transition Time t
Input Capacitance C
Three-State Output

Capacitance
Power Dissipation Capacitance

(Notes 4, 5)

NOTES:

8. C

is used to determine the dynamic power consumption, per channel.

PD

9. PD = V

2

fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

PHL

t

PHL, tPLHCL

t

PHZ, tPLZ

THL

t

PHL, tPLHCL

t

PHL, tPLHCL

t

PHZ, tPLZ

THL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDITIONS VCC(V)

, t

PLHCL

= 50pF

C

= 15pF 5 - 7 - - - - - ns

L

C

= 50pF 6 - - 15 - 20 - 23 ns

L

= 50pF 2 - - 150 - 190 - 225 ns

C

= 15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 26 - 33 - 38 ns

L

CL = 50pF 2 - - 150 - 190 - 225 ns

C

= 15pF 5 - 12 - - - - - ns

L

C

= 50pF 6 - - 26 - 33 - 38 ns

L

, t

IN

C

O

C

PD

CL = 50pF 2 - - 60 - 75 - 90 ns

TLH

CL = 50pF - 10 - 10 - 10 - 10 pF

- - - - 20 - 20 - 20 pF

- 5 -38- - - - - pF

= 50pF 4.5 - - 22 - 28 - 33 ns

C

= 15pF 5 - 9 - - - - - ns

L

= 50pF 4.5 - - 30 - 38 - 45 ns

C

= 15pF 5 - 12 - - - - - ns

L

CL = 50pF 4.5 - - 30 - 38 - 45 ns
C

= 15pF 5 - 12 - - - - - ns

L

, t

IN

C

O

C

PD

CL = 50pF 4.5 - - 12 - 15 - 18 ns

TLH

CL = 50pF - 10 - 10 - 10 - 10 pF

- - - - 20 - 20 - 20 pF

- 5 -41- - - - - pF

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

2 - - 90 - 115 - 135 ns

4.5 - - 18 - 23 - 27 ns

4.5 - - 30 - 38 - 45 ns

4.5 - - 30 - 38 - 45 ns

4.5 - - 12 - 15 - 18 ns
6 - - 10 - 13 - 15 ns

5

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

CD74HC640, CD74HCT640CD74HC640, CD74HCT640

tr = 6ns

V

CC

GND

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 7. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 9. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 8. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

PZH

6ns

PZL

1.3V

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

f

10%

90%

2.7

1.3

OUTPUTS

DISABLED

FIGURE 10. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 11. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

6

7

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