Texas Instruments CD74HCT563M, CD74HCT563E, CD74HCT533E, CD74HC533E, CD74HC563M Datasheet

CD74HC533, CD74HCT533,

[ /Title
(CD74H
C533,
CD74H
CT533,
CD74H
C563,
CD74H
CT563)
/Subject
(High
Speed

Data sheet acquired from Harris Semiconductor
SCHS187

January 1998

Features

• Common Latch-Enable Control

• Common Three-State Output Enable Control

• Buffered Inputs

• Three-State Outputs

• Bus Line Driving Capacity

• Typical Propagation Delay = 13ns at V
C

= 15pF, TA = 25oC (Data to Output)

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

CD74HC563, CD74HCT563

High Speed CMOS Logic Octal Inverting

Transparent Latch, Three-State Outputs

Description

The Harris CD74HC533, CD74HCT533, CD74HC563, and
CD74HCT563 are high speed Octal Transparent Latches
manufactured with silicon gate CMOS technology. They pos­sess the low power consumption of standard CMOS inte­grated circuits, as well as the ability to drive 15 LSTTL
devices.

The outputs are transparent to the inputs when the latch

C to 125oC

CC

OH

enable (
data is latched. The output enable (
state outputs. When the output enable (
outputs are in the high impedance state. The latch operation
is independent to the state of the output enable.

The CD74HC533 and CD74HCT533 are identical in function
to the CD74HC563 and CD74HCT563 but have different
pinouts. The CD74HC533 and CD74HCT533 are similar to
the CD74HC373 and CD74HCT373; the latter are non­inverting types.

Ordering Information

NOTES:

LE) is high. When the latch enable (LE) goes lo w the

OE) controls the three-

OE) is high the

TEMP. RANGE

PART NUMBER

CD74HC533E -55 to 125 20 Ld PDIP F20.3
CD74HCT533E -55 to 125 20 Ld PDIP E20.3
CD74HC563E -55 to 125 20 Ld PDIP E20.3
CD74HCT563E -55 to 125 20 Ld PDIP E20.3
CD74HCT563M -55 to 125 20 Ld SOIC M20.3

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number are available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

(oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1599.1

Pinouts

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

CD74HC533, CD74HCT533

(PDIP, SOIC)

TOP VIEW

1

OE

Q0

2

D0

3

D1

4

Q1

5

Q2

6

D2

7
8

D3

9

Q3

GND

10

Functional Block Diagram

LE

D

0

D
G

D

O

CD74HC563, CD74HCT563

(PDIP, SOIC)

TOP VIEW

V

20

CC

Q7

19

D7

18

D6

17

Q6

16

Q5

15

D5

14

D4

13
12

Q4

11

LE 11

OE

D0
D1
D2
D3
D4
D5
D6
D7

GND

1
2
3
4
5
6
7
8
9

10

CD74HC/HCT533

1

D

2

O

D
G

D

3

O

D
G

D

4

O

D
G

D

5

O

D
G

D

6

O

D
G

D
G

V

20

CC

Q0

19

Q1

18

Q2

17

Q3

16

Q4

15

Q5

14

Q6

13
12

Q7
LE

D

7

O

O

D
G

OE

O

0

O

1

O

2

O

3

O

4

O

5

O

6

O

7

TRUTH TABLE

OUTPUT ENABLE LATCH ENABLE DATA Q OUTPUT

LHHL
LHLH
LLlH
LLhL

HXXZ

NOTE: H = High Voltage Level, L = Low VoltageLevel, X = Don’t Care, Z = High Impedance State, l = Low voltage level one set-up time prior
to the high to low latch enable transition, h = High voltage level one set-up time prior to the high to low latch enable transition.

2

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

VCC (V)

o

25

C -40oC TO 85oC -55oC TO 125oC

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSV

3

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Three-State Leakage

-V

Current

HCT TYPES

High Level Input

V

IH

Voltage
Low Level Input

Voltage
High Level Output

Voltage

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage

I

I

I

CC

-V

Current

Additional Quiescent
Device Current Per

∆I

CC

Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

or

IL

V

VO =

VCCor

IH

GND

- - 4.5 to

- - 4.5 to

VIH or

V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

-6 4.5 3.98 - - 3.84 - 3.7 - V

VIH or

V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

IL

6 4.5 - - 0.26 - 0.33 - 0.4 V

VCC to

- 5.5 - - ±0.1 - ±1-±1µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

or

IL

V

VO =

VCCor

IH

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

25

VCC (V)

6--±0.5 - ±5-±10 µA

2-- 2 - 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

5.5 - - ±0.5 - ±5-±10 µA

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

D0 - D7 0.15

LE 0.30

OE 0.55

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Specifica­tions table, e.g., 360µA max at 25oC.

4

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Prerequisite For Switching Specifications

TEST

PARAMETER SYMBOL

HC TYPES

LE Pulse Width t

Set-up Time Data to

Hold Time, Data to

LE t

LE

(533)

Hold Time, Data to

LE

(563)

HCT TYPES

LE Pulse Width t
Set-up Time Data to
Hold Time, Data to
Hold Time, Data to

LE t
LE (533) t
LE (563) t

SU

t

t

CONDITIONS

W

H

H

w
w
H
H

o

C -40oC TO 85oC -55oCTO125oC

V

CC

(V)

25

UNITSMIN TYP MAX MIN MAX MIN MAX

- 2 80 - - 100 - 120 - ns

4.5 16 - - 20 - 24 - ns
6 14 - - 17 - 20 - ns

- 2 50 - - 65 - 75 - ns

4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns

- 2 35 - - 45 - 55 - ns

4.5 7 - - 9 - 11 - ns
66--8-7-ns

-24--4-4-ns

4.5 4 - - 4 - 4 - ns
64--4-4-ns

- 4.5 16 - - 20 - 24 - ns

- 4.5 10 - - 13 - 15 - ns

- 4.5 8 - - 10 - 12 - ns

- 4.5 5 - - 5 - 5 - ns

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Data to Qn
(HC533)

Propagation Delay,
Data to Qn
(HC563)

Propagation Delay,
LE to Qn
(HC533)

Propagation Delay,
LE to Qn
(HC563)

, t

t

PLH

PHL

t

PLH,tPHL

t

PLH,tPHL

t

PLH,tPHL

, tf = 6ns

r

-55oC TO
125oC

TEST

o

25

C -40oC TO 85oC

CONDITIONS VCC (V)

CL= 50pF 2 - 165 205 250 ns

4.5 - 33 41 50 ns
6 - 28 35 43 ns

= 15pF 5 13 - - - ns

C

L

CL= 50pF 2 - 150 190 225 ns

4.5 - 30 38 45 ns
6 - 26 33 38 ns

= 15pF 5 12 - - - ns

C

L

CL= 50pF 2 - 175 220 265 ns

4.5 - 35 44 53 ns
6 - 30 37 45 ns

= 15pF 5 14 - - - ns

C

L

CL= 50pF 2 - 165 205 250 ns

4.5 - 33 41 50 ns
6 - 28 35 43 ns

= 15pF 5 13 - - - ns

C

L

UNITSTYP MAX MAX MAX

5

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Switching Specifications Input t

PARAMETER SYMBOL

Enable Times
(HC533)

Disable Times
(HC533)

Enable and Disable Times
(HC563)

Input Capacitance C
Three-State Output

Capacitance
Power Dissipation

Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay,
Data to Qn
(HC/HCT533)

Propagation Delay,
Data to Qn
(HC/HCT563)

Propagation Delay,
LE to Qn
(HC/HCT533)

Propagation Delay,
LE to Qn
(HC/HCT563)

Enable Times
(HC/HCT533)

Disable Times
(HC/HCT533)

Enable and Disable Times
(HC/HCT563)

Input Capacitance C
Power Dissipation

Capacitance
(Notes 5, 6)

NOTES:

5. C

is used to determine the no-load dynamic power consumption, per latch.

PD

6. PD (total power per latch) = CPD V
Capacitance, VCC = Supply Voltage.

t

PZH,tPZL

t

PHZ,tPLZ

t

PZH,tPZL,

t

PHZ,tPLZ

I

C

O

C

PD

, t

t

PLH

PHL

t

, t

PLH

PHL

t

, t

PLH

PHL

t

, t

PZL

PZH

t

, t

PLZ

PZH

, t

t

TLH

THL

t

PZH,tPZL,

t

PHZ,tPLZ

I

C

PD

, tf = 6ns (Continued)

r

TEST

CONDITIONS VCC (V)

CL= 50pF 2 - 150 190 225 ns

= 15pF 5 12 - - - ns

C

L

CL= 50pF 2 - 150 190 225 ns

= 15pF 5 12 - - - ns

C

L

CL= 50pF 2 - 150 190 225 ns

C

= 15pF 5 12 - - - ns

L

---1010 10pF

---2020 20pF

- 5 42 - - - pF

CL= 50pF 4.5 - 34 43 51 ns

= 15pF 5 14 - - - ns

C

L

CL= 50pF 4.5 - 30 38 45 ns
C

= 15pF 5 12 - - - ns

L

CL= 50pF 4.5 - 38 48 57 ns

= 15pF 5 16 - - - ns

C

L

CL= 50pF 4.5 - 35 44 53 ns

= 15pF 5 14 - - - ns

C

L

CL= 50pF 4.5 - 35 44 53 ns

= 15pF 5 14 - - - ns

C

L

CL= 50pF 4.5 - 30 38 45 ns

= 15pF 5 12 - - - ns

C

L

CL= 50pF 4.5 - 35 44 53 ns

= 15pF 5 14 - - - ns

C

L

---1010 10pF

- 5 42 - - - pF

2

fi + Σ CLV

CC

CC

2

o

C -40oC TO 85oC

25

-55oC TO
125oC

4.5 - 30 38 45 ns
6 - 26 33 38 ns

4.5 - 30 38 45 ns
6 - 26 33 38 ns

4.5 - 30 38 45 ns
6 - 26 33 38 ns

fo where fi = Input Frequency, fo = Output Frequency, CL = Output Load

UNITSTYP MAX MAX MAX

6

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

fC

50%

1.3V

I

fC

L

3V

GND

+ tWH=

t

t

WL

WH

I

L

V

CC

GND

t

rCL

CLOCK

= 6ns

0.3V

2.7V

1.3V

0.3V

= 6ns

t

fCL

1.3V

t

WL

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

90%
50%
10%

THL

90%

t

PLH

50%

10%

INVERTING

OUTPUT

t

PHL

FIGURE 3. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tfC

L

V

CC

50%

GND

t

H(L)

V

CC

50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table.For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

3V

1.3V
GND

t

H(L)

3V

1.3V

t

SU(L)

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V

SET, RESET

1.3V

90%

1.3V
t

t

PLH

TLH

90%

1.3V
10%

t

PHL

t

THL

OR PRESET

IC

C

L

50pF

FIGURE 6. HCTSETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

GND

CD74HC533, CD74HCT533, CD74HC563, CD74HCT563

Test Circuits and Waveforms

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

90%

10%

90%

OUTPUTS

DISABLED

(Continued)

10%

t

PZL

t

PZH

FIGURE 7. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

50%

50%

OUTPUTS
ENABLED

IC WITH

THREE-

STATE

OUTPUT

V

CC

GND

OUTPUT
R

0.3

t

t

6ns

PZL

PZH

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 8. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

3V

GND

1.3V

1.3V
OUTPUTS

ENABLED

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 9. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

and t

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

PZL

8

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