1
Data sheet acquired from Harris Semiconductor
SCHS199
February 1998
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
File Number 1917.1
CD74HC4016
High-Speed CMOS Logic
Quad Bilateral Switch
Features
• Wide Analog-Input-Voltage Range . . . . . . . . .0V to 10V
• Low “ON” Resistance
-45Ω (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . .V
CC
= 4.5V
-35Ω (Typ). . . . . . . . . . . . . . . . . . . . . . . . . . . . V
CC
= 6V
-30Ω (Typ). . . . . . . . . . . . . . . . . . . . . . . . . .1fcV
CC
= 9V
• Fast Switching and Propagation Delay Times
• Low “OFF” Leakage Current
• Built-In “Break-Before-Make” Switching
• Suitable for Sample and Hold Applications
• Wide Operating Temperature Range . . . -55
o
C to 125oC
• HC Types
- 2V to 10V Operation
- High Noise Immunity: N
IL
= 30%, NIH = 30% of V
CC
at VCC = 5V
Description
The Harris CD74HC4016 contains four independent digitally
controlled analog switches that use silicon-gate CMOS
technology to achieve operating speeds similar to LSTTL
with the low power consumption of standard CMOS
integrated circuits.
Each switch has two input/output terminals (nY, nZ) and an
active high enable input (nE). Current through the switch will
not cause additional V
CC
current provided the analog
voltage is maintained between V
CC
and GND.
Pinout
CD74HC4016
(PDIP)
TOP VIEW
Ordering Information
PART NUMBER
TEMP. RANGE
(oC) PACKAGE
PKG.
NO.
CD74HC4016E -55 to 125 14 Ld PDIP E14.3
CD74HC4016E -55 to 125 14 Ld SOIC M14.15
NOTES:
1. When ordering, use the entire part number.Add thesuffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
1Y
1Z
2Z
2Y
2E
3E
GND
V
CC
1E
4E
4Y
4Z
3Z
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
[ /Title
(CD74
HC4016
)
/
Sub-
j
ect
(HighSpeed
CMOS
Logic
Quad
Bilat-
2
Functional Diagram
Logic Diagram
TRUTH TABLE
INPUT
nE SWITCH
L OFF
HON
NOTE:
H = High Level Voltage
L = Low Level Voltage
1
2
4
3
9
10
11
8
13
5
12
6
4E
3E
2E
1E
1Y
1Z
2Y
2Z
3Y
3Z
4Y
4Z
V
CC
= 14
GND = 7
V
CC
GND
nZ
nY
nE
CD74HC4016CD74HC4016
3
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Drain Current, per Output, I
O
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 10V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
9V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 250ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) VIS(V) VCC (V) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input
Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
“ON” Resistance
IO = 1mA
R
ON
VIH or
V
IL
VCC or
GND
4.5 - 45 180 - 225 - 270 Ω
6 - 35 160 - 200 - 240 Ω
9 - 30 135 - 170 - 205 Ω
4.5 - 85 320 - 400 - 480 Ω
6 - 55 240 - 300 - 360 Ω
9 - 35 170 - 215 - 255 Ω
Maximum “ON”
Resistance Between
Any Two Switches
∆R
ON
VIL or
V
IH
VCC or
GND
4.5-10-----Ω
6-8.5-----Ω
Switch Off Leakage
Current
I
IZ
En =
GND
VCC or
GND
6--±0.1 - ±1-±1 µA
10 - - ±0.1 - ±1-±1 µA
Logic Input Leakage
Current
I
I
VCC or
GND
-6--±0.1 - ±1-±1 µA
CD74HC4016CD74HC4016
4
Quiescent Device
Current
IO = 0mA
I
CC
VCC or
GND
VCC or
GND
6--2- 20 - 40µA
10 - - 16 - 160 - 320 µA
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) VIS(V) VCC (V) MIN TYP MAX MIN MAX MIN MAX
Switching Specifications Input t
r
, tf = 6ns
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC TYPES
Propagation Delay,
Switch In to Switch Out
t
PLH
, t
PHL
CL= 50pF 2 - - 60 - 75 - 90 ns
4.5 - - 12 - 15 - 18 ns
CL= 15pF 5 - 4 - ----ns
CL= 50pF 6 - - 10 - 13 - 15 ns
9 - - 8 - 10 - 12 ns
Propagation Delay,
Switch Turn-On En to Out
t
PZH,tPZL
CL= 50pF 2 - - 190 - 240 - 285 ns
4.5 - - 38 - 48 - 57 ns
CL= 15pF 5 - 16 - ----ns
CL= 50pF 6 - - 32 - 41 - 48 ns
9 - - 28 - 35 - 42 ns
Propagation Delay,
Switch Turn-Off En to Out
t
PHZ,tPLZ
CL= 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
CL= 15pF 5 - 12 - ----ns
CL= 50pF 6 - - 25 - 31 - 38 ns
9 - - 22 - 28 - 33 ns
Input Capacitance C
I
- - - - 10 - 10 - 10 pF
Power Dissipation Capacitance
(Notes 4, 5)
C
PD
- 5-12-----pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per package.
5. PD=CPDV
CC
2
fi+ Σ (CL+CS)V
CC
2
fowhere fi= input frequency, fo= output frequency, CL= output load capacitance, CS= switch
capacitance, VCC = supply voltage.
Analog Channel Specifications T
A
= 25oC
PARAMETER TEST CONDITIONS VCC (V) CD74HC4016 UNITS
Switch Frequency Response Bandwidth at -3dB
Figure 3
Figure 6, Notes 6, 7 4.5 >200 MHz
Crosstalk Between Any Two Switches, Figure 4 Figure 5, Notes 7, 8 4.5 TBE dB
Total Harmonic Distortion 1kHz, VIS = 4V
P-P
Figure 7
4, 5 0.078 %
1kHz, VIS = 8V
P-P
Figure 7
9 0.018 %
CD74HC4016CD74HC4016
5
Control to Switch Feedthrough Noise Figure 8 4.5 TBE mV
9 TBE mV
Switch “OFF” Signal Feedthrough, Figure 4 Figure 9, Notes 7, 8 4.5 -62 dB
Switch Input Capacitance, C
S
-5pF
NOTES:
6. Adjust input level for 0dBm at output, f = 1MHz.
7. VIS is centered at VCC/2.
8. Adjust input for 0dBm at VIS.
Analog Channel Specifications T
A
= 25oC (Continued)
PARAMETER TEST CONDITIONS VCC (V) CD74HC4016 UNITS
Typical Performance Curves
FIGURE 1. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE
FIGURE 2. TYPICAL “ON” RESISTANCE vs INPUT SIGNAL
VOLTAGE
FIGURE 3. SWITCH FREQUENCY RESPONSE FIGURE 4. SWITCH-OFF SIGNAL FEEDTHROUGH AND
CROSSTALK vs FREQUENCY
110
100
90
80
70
60
50
40
30
20
10
01 23 454.5
INPUT SIGNAL VOLTAGE, V
IS
(V)
“ON” RESISTANCE, R
ON
(Ω)
6
VCC = 6V
VCC = 4.5V
0
50
45
40
35
30
25
20
15
10
01 2 3 4 65
INPUT SIGNAL VOLTAGE, V
IS
(V)
“ON” RESISTANCE, R
ON
(Ω)
7
VCC = 9V
89
5
0
60
0
-1
-2
-3
-4
10K 100K 1M 10M 100M
FREQUENCY (f), Hz
CHANNEL ON BANDWIDTH, dB
CL = 10pF
V
CC
= 4.5V
R
L
= 50Ω
T
A
= 25oC
PIN 4 TO 3
CL = 10pF
V
CC
= 9V
R
L
= 50Ω
T
A
= 25oC
PIN 4 TO 3
0
-20
-40
-60
-80
10K 100K 1M 10M 100M
FREQUENCY (f), Hz
CROSSTALK, dB
CL = 10pF
V
CC
= 4.5V
RL = 50Ω
T
A
= 25oC
PIN 4 TO 3
CL = 10pF
V
CC
= 9V
RL = 50Ω
T
A
= 25oC
PIN 4 TO 3
SWITCH OFF SIGNAL FEEDTHROUGH, dB
-100
CD74HC4016CD74HC4016
6
Analog Test Circuits
FIGURE 5. CROSSTALK BETWEEN TWO SWITCHES TEST CIRCUIT
FIGURE 6. FREQUENCY RESPONSE TEST CIRCUIT FIGURE 7. TOTAL HARMONIC DISTORTION TEST CIRCUIT
FIGURE 8. CONTROL-TO-SWITCH FEEDTHROUGH NOISE
TEST CIRCUIT
FIGURE 9. SWITCH OFF SIGNAL FEEDTHROUGH
V
CC
V
IS
0.1µF
RC
V
CC
/2
V
OS1
SWITCH
ON
V
CC
VCC/2
R
RC
V
CC
/2
V
OS2
SWITCH
ON
dB
METER
V
IS
fIS = 1MHz SINEWAVE
R = 50Ω
C = 10pF
R
V
CC
V
IS
0.1µF
50Ω 10pF
V
CC
/2
V
OS
SWITCH
ON
dB
METER
V
CC
V
IS
10µF
10kΩ 50pF
V
CC
/2
V
OS
SWITCH
ON
DISTORTION
METER
VI = V
IH
fIS = 1kHz TO 10kHz
V
IS
SINE
WAVE
SWITCH
ALTERNATING
ON AND OFF
t
r
, tf≤ 6ns
f
CONT
= 1MHz
50% DUTY
CYCLE
SCOPE
V
P-P
V
OS
E
V
OS
50pF
600Ω
V
CC
/2
600Ω
V
CC
/2
V
CC
V
CC
V
IS
0.1µF
RC
V
CC
/2
V
OS
SWITCH
ON
dB
METER
R
V
CC
/2
VC = V
IL
fIS≥ 1MHz SINEWAVE
R = 50Ω
C = 10pF
Test Circuits and Waveforms
FIGURE 10. HC/HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
FIGURE 11. SWITCH TURN-ON AND TURN OFF
PROPAGATION DELAY TIMES
t
PHL
t
PLH
t
THL
t
TLH
90%
50%
10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
(HC)
tr = 6ns tf = 6ns
90%
3V (HCT)
50%
10%
90%
GND
10%
90%
50%
50%
OUTPUT
DISABLE
OUTPUT LOW
TO OFF
OUTPUT HIGH
TO OFF
OUTPUTS
ENABLED
OUTPUTS
DISABLED
OUTPUTS
ENABLED
6ns 6ns
t
PZH
t
PHZ
t
PZL
t
PLZ
VCC(HC)
3V (HCT)
CD74HC4016CD74HC4016
IMPORTANT NOTICE
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any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
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pertaining to warranty, patent infringement, and limitation of liability.
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
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DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
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Copyright 1998, Texas Instruments Incorporated
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