Data sheet acquired from Harris Semiconductor
/
j
SCHS198
November 1997
CD74HC4015
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
[ /Title
(CD74
HC401
5)
Subect
(High
Speed
CMOS
Logic
Dual
4-
Features
• Maximum Frequency, Typically 60MHz
C
= 15pF, VCC = 5V, TA = 25oC
L
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
C to 125oC
Description
The Harris CD74HC4015 consists of two identical,
independent, 4-stage serial-input/parallel-output registers.
Each register has independent Clock (CP) and Reset (MR)
inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All
register stages are D-type, master-slave flip-flops. The logic
level present at the Data input is transferred into the first
register stage and shifted over one stage at each positivegoing clock transition. Resetting of all stages is
accomplished by a high level on the reset line.
The devicecan drive up to 10 low power Schottky equivalent
loads. The CD74HC4015 is an enhanced version of
equivalent CMOS types.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CC
CD74HC4015E -55 to 125 20 Ld PDIP E16.3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or dieforthis part numberis available which meetsall electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
PKG.
NO.
Pinout
CD74HC4015
(PDIP)
TOP VIEW
V
1
2CP
2
2Q
3
3
1Q
2
4
1Q
1
5
1Q
0
6
1MR
1D
7
8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
16
CC
2D
15
14
2MR
13
2Q
0
12
2Q
1
11
2Q
2
10
1Q
3
9
1CP
File Number 1678.1
Functional Diagram
CD74HC4015
1D
1CP
1MR
2D
2CP
2MR
7
9
6
15
1
14
5
1Q
4
1Q
3
1Q
10
1Q
13
2Q
12
2Q
11
2Q
2
2Q
GND = 8
= 16
V
CC
0
1
2
3
0
1
2
3
TRUTH TABLE
INPUTS OUTPUTS
CP D R Q
0
↑ lLLq’0q’
↑ hLHq’0q’
↓ XLq’0q’
Q
1
1
Q
2
1
1
q’
2
Q
3
q’
2
q’
2
q’
3
XXHLLLL
NOTES:
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’n= Lower caseletters indicate the state of the referenced output one set-up time prior tothe Lowto High
clock transition.
2
CD74HC4015
t6
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC - Lead Tips Only)
CC
f
DC Electrical Specifications
TEST
PARAMETER SYMBOL
High Level Input
Voltage
CONDITIONS
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
V
CC
(V)
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input
Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output
Voltage
CMOS Loads
V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
OH
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output
Voltage
TTL Loads
- - ---- - - -V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output
Voltage
CMOS Loads
V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
OL
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output
Voltage
TTL Loads
- - ---- - - -V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage
Current
Quiescent Device
Current
I
VCC or
I
-6--±0.1 - ±1-±1 µA
GND
I
CC
VCC or
0 6 - - 8 - 80 - 160 µA
GND
NOTE: For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.
25oC -40oC TO 85oC -55oC TO 125oC
UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
3
Prerequisite for Switching Specifications
PARAMETER SYMBOL VCC (V)
Maximum Clock
Frequency
Clock Pulse Width t
MR Pulse Width t
MR Recovery Time t
Set-up Time,
Data-In to CP
Hold Time,
Data-In to CP
f
MAX
W
W
REC
t
SUL,tSUH
t
H
26-5-4-MHz
4.5 30 - 24 - 20 - MHz
6 35 - 28 - 24 - MHz
2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
2 150 - 190 - 225 - ns
4.5 30 - 38 - 45 - ns
626-33-38-ns
250-65-75-ns
4.5 10 - 13 - 15 - ns
6 9 - 11 - 13 - ns
260-75-90-ns
4.5 12 - 15 - 18 - ns
610-13-15-ns
20-0-0-ns
4.5 0 - 0 - 0 - ns
60-0-0-ns
CD74HC4015
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
Switching Specifications Input t
PARAMETER SYMBOL
Propagation Delay (Figure 1) t
Clock to Q
n
PLH,
t
PHL
, tf = 6ns
r
TEST
CONDITIONS
V
CC
(V)
CL= 50pF 2 - - 175 - 220 - 270 ns
4.5 - - 35 - 44 - 54 ns
CL=15pF 5 - 14 - - - - - ns
CL= 50pF 6 - - 30 - 37 - 46 ns
MR to Qn, (Clock High) t
PLH,
t
PHL
CL= 50pF 2 - - 275 - 345 - 415 ns
4.5 - - 55 - 64 - 83 ns
CL=15pF 25 - - - - - ns
CL= 50pF 6 - - 47 - 54 - 71 ns
MR to Qn, (Clock Low) t
PLH,
t
PHL
CL= 50pF 2 - - 325 - 400 - 490 ns
4.5 - - 65 - 81 - 98 ns
CL=15pF 25 - - - - - ns
CL= 50pF 6 - - 55 - 69 - 83 ns
Output Transition Time
(Figure 1)
t
TLH,tTHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns
Input Capacitance C
Maximum Clock Frequency f
Power Dissipation
MAX
C
CL= 50pF - - - 10 - 10 - 10 pF
IN
CL=15pF 5 - 60 - - - - - MHz
CL=15pF 5 - 43 - - - - - pF
PD
Capacitance
(Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per shift register.
5. PD = V
2
fi+ ∑ CL V
CC
2
where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.
CC
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
4
Test Circuit and Waveform
CD74HC4015
90%
t
PLH
IC
t
TLH
tfC
L
50%
t
H(L)
t
SU(L)
t
THL
90%
50%
10%
t
PHL
C
L
50pF
V
CC
GND
V
CC
50%
GND
GND
CLOCK
INPUT
DAT A
INPUT
t
SU(H)
OUTPUT
t
REM
V
CC
SET, RESET
OR PRESET
trC
L
90%
10%
t
H(H)
50%
FIGURE 1. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED
SEQUENTIAL LOGIC CIRCUITS
5
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