Texas Instruments CD74HC4015M, CD74HC4015E, CD54HC4015F3A Datasheet
Data sheet acquired from Harris Semiconductor
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SCHS198
November 1997
CD74HC4015
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
[ /Title
(CD74
HC401
5)
Subect
(High
Speed
CMOS
Logic
Dual
4-
Features
• Maximum Frequency, Typically 60MHz
C
= 15pF, VCC = 5V, TA = 25oC
L
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
o
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
= 30%, NIH = 30% of V
IL
at VCC = 5V
C to 125oC
Description
The Harris CD74HC4015 consists of two identical,
independent, 4-stage serial-input/parallel-output registers.
Each register has independent Clock (CP) and Reset (MR)
inputs as well as a single serial Data input. “Q” outputs are
available from each of the four stages on both registers. All
register stages are D-type, master-slave flip-flops. The logic
level present at the Data input is transferred into the first
register stage and shifted over one stage at each positivegoing clock transition. Resetting of all stages is
accomplished by a high level on the reset line.
The devicecan drive up to 10 low power Schottky equivalent
loads. The CD74HC4015 is an enhanced version of
equivalent CMOS types.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
CC
CD74HC4015E -55 to 125 20 Ld PDIP E16.3
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer or dieforthis part numberis available which meetsall electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
PKG.
NO.
Pinout
CD74HC4015
(PDIP)
TOP VIEW
V
1
2CP
2
2Q
3
3
1Q
2
4
1Q
1
5
1Q
0
6
1MR
1D
7
8
GND
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
16
CC
2D
15
14
2MR
13
2Q
0
12
2Q
1
11
2Q
2
10
1Q
3
9
1CP
File Number 1678.1
Functional Diagram
CD74HC4015
1D
1CP
1MR
2D
2CP
2MR
7
9
6
15
1
14
5
1Q
4
1Q
3
1Q
10
1Q
13
2Q
12
2Q
11
2Q
2
2Q
GND = 8
= 16
V
CC
0
1
2
3
0
1
2
3
TRUTH TABLE
INPUTS OUTPUTS
CP D R Q
0
↑ lLLq’0q’
↑ hLHq’0q’
↓ XLq’0q’
Q
1
1
Q
2
1
1
q’
2
Q
3
q’
2
q’
2
q’
3
XXHLLLL
NOTES:
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior to the Low to High Clock Transition
L = Low Voltage Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
X = Don’t Care.
↑ = Low to High Clock Transition
↓ = High to Low Clock Transition
q’n= Lower caseletters indicate the state of the referenced output one set-up time prior tothe Lowto High
clock transition.
2
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