Texas Instruments CD74HCT257M96, CD74HCT257M, CD74HCT257E, CD74HC257M, CD74HC257E Datasheet

CD74HC257,

/
j

[ /Title
(CD74
HC257
,
CD74
HCT25

7)
Sub­ect

(High
Speed
CMOS
Logic
Quad
2-Input
Multi­plexer

Data sheet acquired from Harris Semiconductor
SCHS171

November 1997

Multiplexer with Three-State Non-In verting Outputs

Features

• Buffered Inputs

• Typical Propagation Delay ( In to Output ) = 12ns at
V

= 5V, CL = 15pF, TA = 25oC

CC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

C to 125oC

OH

CD74HCT257

High Speed CMOS Logic Quad 2-Input

Description

The Harris CD74HC257 and CD74HCT257 are quad 2-input
multiplexers which select four bits of data from two sources
under the control of a common Select Input (S). The Output
Enable input (
the outputs (1Y-4Y) are in the high impedance state regard­less of all other input conditions.

Moving data from two groups of registers to four common
output busses is a common use of the 257. The state of the
Select input determines the particular register from which
the data comes. It can also be used as a function generator.

Ordering Information

CC

PART NUMBER

CD74HC257E -55 to 125 16 Ld PDIP E16.3
CD74HCT257E -55 to 125 16 Ld PDIP E16.3
CD74HC257M -55 to 125 16 Ld SOIC M16.15
CD74HCT257M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer or die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

OE) is active LOW. When OE is HIGH, all of

TEMP. RANGE

(oC) PACKAGE

PKG.

NO.

Pinout

CD74HC257, CD74HC257

(PDIP, SOIC)

TOP VIEW

V

1

S

2

1I

0

3

1I

1

4

1Y

5

2I

0

6

2I

1

2Y

7
8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

16

CC

15

OE

14

4I

0

13

4I

1

12

4Y
3I

11

0

10

3I

1

9

3Y

File Number 1650.1

Functional Diagram

15

OE

1

S

13

4I

1

14

4I

0

CD74HC257, CD74HCT257

P

N

12

4Y

3I

1

3I

0

2I

1

2I

0

1I

1

1I

0

10
11

6
5

3
2

3 CIRCUITS IDENTICAL TO CIRCUIT

IN ABOVE DASHED ENCLOSURE

TRUTH TABLE

OUTPUT
ENABLE

OE S I

SELECT

INPUT DATA INPUTS OUTPUT

0

I

1

Y

HXXXZ

LLLXL
LLHXH
LHXLL

9

7

4

3Y

2Y

1Y

LHXHH

NOTE:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
Z = High Impedance, OFF State

2

CD74HC257, CD74HCT257

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC257, CD74HCT257

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

Three-State Leakage
Current

I

I

CC

OZ

VCC or

GND

VIL or

V

IH

VCC (V)

0 6 - - 8 - 80 - 160 µA

-6--±0.5 - ±5-±10 µA

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

VCC to

I

0 5.5 - - ±0.1 - ±1-±1 µA

GND

I

CC

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5
Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage
Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5-±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

Data 0.95

S3

OE 0.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

4

CD74HC257, CD74HCT257

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS VCC (V)

HC TYPES

Propagation Delay
In to Y

t

PLH

, t

PHLCL

= 50pF 2 - 150 190 225 ns

4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
CL = 50pF 6 - 26 33 38 ns

Propagation Delay
S to Y

t

PLH

, t

PHLCL

= 50pF 2 - 175 220 265 ns

4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
CL = 50pF 6 - 30 37 45 ns

Propagation Delay
OE to Y

t

PLZ

t

PZL

, t

,

CL = 50pF 2 - 150 190 225 ns

PHZ

, t

PZH

CL= 50pF 4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
CL = 50pF 6 - 26 33 38 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns

6 - 10 13 15 ns
Input Capacitance C
Three-State Output

I

C

O

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 45 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay
In to Y

Propagation Delay
S to Y

Propagation Delay
OE to Y

Output Transition Times t
Input Capacitance C
Three-State Output

t

, t

PLH

PHLCL

t

PZL,tPZHCL

t

, t

PLZ

PHZCL

, t

TLH

THLCL

I

C

O

= 50pF 4.5 - 33 41 50 ns

CL= 15pF 5 13 - - - ns

= 50pF 4.5 - 38 48 57 ns

CL= 15pF 5 12 - - - ns

= 50pF 4.5 - 30 38 45 ns

CL= 15pF 5 16 - - - ns

= 50pF 4.5 - 12 15 18 ns

---1010 10pF

---2020 20pF
Capacitance

Power Dissipation

C

PD

- 5 45 - - - pF
Capacitance
(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per multiplexer.

6. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

5

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

CD74HC257, CD74HCT257

tr = 6ns

V

CC

GND

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

6ns

PZL

1.3V

PZH

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT
R

= 1kΩ

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩ to

6

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