Texas Instruments CD74HCT243M, CD74HCT243E, CD74HC243M96, CD54HCT243F3A, CD54HC243F3A Datasheet

CD74HCT242 was not acquired from Harris Semiconductor.

/
j

Data sheet acquired from Harris Semiconductor
SCHS168

November 1997

Quad-Bus Transceiver with Three-State Outputs

CD74HCT242, CD74HC243,

CD74HCT243

High Speed CMOS Logic

[ /Title
(CD74
HCT24
2,
CD74
HC243
,
CD74
HCT24

3)
Sub­ect

(High
Speed
CMOS
Logic
Quad-

Features

• Typical Propagation Delay (A to B, B to A) of 7ns at
V

= 5V, CL = 15pF, TA = 25oC

CC

• Three-State Outputs

• Buffered Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

o

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

C to 125oC

OH

Pinout

CD74HCT242, CD74HC243, CD74HCT243

(PDIP, SOIC)

TOP VIEW

OEB

NC

A0
A1
A2
A3

GND

1
2
3
4
5
6
7

V

14

CC

OEA

13

NC

12

B0

11

B1

10

B2

9

B3

8

Description

The Harris CD74HCT242, CD74HC243 and CD74HCT243
silicon-gate CMOS three-state bidirectional inverting and
non-inverting buffers are intended for two-wayasynchronous
communication between data buses. They have high drive
current outputs which enable high-speed operation when
driving large bus capacitances. These circuits possess the
low power dissipation of CMOS circuits, and have speeds
comparable to low power Schottky TTL circuits. They can
drive 15 LSTTL loads.

The CD74HCT242 is an inverting buffer; the CD74HC243
and CD74HCT243 are non-inverting buffers.

The states of the output enables (
both the direction of flow (A to B, B to A), and the three-state
mode.

CC

OEB, OEA) determine

Ordering Information

TEMP. RANGE

PART NUMBER

CD74HC243E -55 to 125 14 Ld PDIP E14.3
CD74HC243M -55 to 125 14 Ld SOIC M14.15
CD74HCT243M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer or diefor this partnumber is availablewhich meets allelec­trical specifications. Please contact your local sales

(oC) PACKAGE

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1488.1

Functional Diagrams

CD74HCT242 CD74HC243, CD74HC243

CD74HCT242, CD74HC243, CD74HCT243

3

A0

4

A1

5

A2

6

A3

1

OEB

13

OEA

CONTROL INPUTS

DIRECTION

SELECT LOGIC

11

B0

10

B1

9

B2

8

B3

A0

A1

A2

A3

OEB
OEA

3

4

5

6

1

13

DIRECTION

SELECT LOGIC

TRUTH TABLE

HCT242 SERIES HC, HCT243 SERIES

DATA PORT STATUS DATA PORT STATUS

11

B0

10

B1

9

B2

8

B3

OEB OEA An Bn An Bn

HHOIOI

LHZZZZ

HLZZZZ

LLIOIO

NOTE:
H = High Voltage Level
L = Low Voltage Level
I = Input
O = Output (Same Level as Input)
O = Output (Inversion of Input Level)
Z = High Impedance
To prev ent e xcess currents in the High Z modes all I/O terminals should be terminated with 10kΩ to 1MΩ resistors.

2

CD74HCT242, CD74HC243, CD74HCT243

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

Low Level Output
Voltage
TTL Loads

6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

3

CD74HCT242, CD74HC243, CD74HCT243

DC Electrical Specifications (Continued)

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL

Input Leakage
Current

Quiescent Device
Current

Three-State Leakage
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

V

(V)

CC

I

VCC or

I

-6--±0.1 - ±1-±1µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

GND

I

CC

VCC or

0 6 - - 8 - 80 - 160 µA

GND

I

OZ

V

VIL or

V

IH

IH

- - 4.5 to

-6--±0.5 - ±0.5 - ±10 µA

2-- 2 - 2 - V

5.5

V

IL

- - 4.5 to

- - 0.8 - 0.8 - 0.8 V

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

VCC to

I

0 5.5 - - ±0.1 - ±1-±1µA

GND

I

CC

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 100 360 - 450 - 490 µA

Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage
Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5.0 - ±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

INPUT UNIT LOADS

An, Bn 1.1

OEA, OEB 0.6

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

4

CD74HCT242, CD74HC243, CD74HCT243

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS V

CC

(V)

HC TYPES

Propagation Delay Data
to Outputs (HC243)

t

PLH

, t

PHLCL

= 50pF 2 - 90 115 135 ns

4.5 - 18 23 27 ns
CL= 15pF 5 7 - - - ns
CL = 50pF 6 - 15 20 23 ns

Output High-Z, to High Level
to Low Level

t

PZL,tPZHCL

= 50pF 2 - 150 190 225 ns
CL = 50pF 4.5 - 30 38 45 ns
CL = 15pF 5 12 - - - ns
CL = 50pF 6 - 26 33 38 ns

Output High Level,
Output Low Level to High-Z

t

PHZ,tPLZCL

= 50pF 2 - 150 190 225 ns
CL = 50pF 4.5 - 30 38 45 ns
CL = 15pF 5 12 - - - ns
CL = 50pF 6 - 26 33 38 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 60 75 90 ns

4.5 - 12 15 18 ns
6 - 10 13 15 ns

Input Capacitance C
Three-State Output

I

C

O

---1010 10pF

---2020 20pF

Capacitance
Power Dissipation

C

PD

- 5 80 - - - pF
Capacitance (HC243)
(Notes 5, 6)

HCT TYPES

Propagation Delay Data to
Outputs (HCT242)

Propagation Delay Data to
Outputs (HCT243)

Output High-Z to High Level
to Low Level

Output High Level,
Output Low Level to High-Z

Output Transition Times t
Input Capacitance C
Three-State Output

t

t

t

t

PLH

PLH

PZH

PHZ

TLH

, t

PHLCL

, t

PHLCL

, t

PZLCL

, t

PLZCL

, t

THLCL

I

C

O

= 50pF 4.5 - 20 25 30 ns

CL= 15pF 5 8 - - - ns

= 50pF 4.5 - 22 28 33 ns

CL= 15pF 5 9 - - - ns

= 50pF 4.5 - 34 43 51 ns

CL= 15pF 5 14 - - - ns

= 50pF 4.5 - 35 44 53 ns

CL= 15pF 5 14 - - - ns

= 50pF 4.5 - 12 15 18 ns

---1010 10pF

---2020 20pF
Capacitance

Power Dissipation
Capacitance
(Notes 5, 6)

C

PD

HCT242 5 90 - - - pF
HCT243 5 91 - - - pF

NOTES:

5. CPD is used to determine the dynamic power consumption, per channel.

6. PD = V

2

fi(CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

25oC -40oC TO 85oC -55oCTO125oC

UNITSTYP MAX MAX MAX

5

CD74HCT242, CD74HC243, CD74HCT243

Test Circuits and Waveforms

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

V

CC

GND

tr = 6ns

INPUT

2.7V

1.3V

0.3V

= 6ns

t

f

3V

GND

INVERTING

OUTPUT

t

THL

t

PHL

t

PLH

50%

10%

90%

t

TLH

FIGURE 1. HC AND HCT TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

OUTPUTS
ENABLED

FIGURE 3. HCTHREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCTTRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

6ns

PZL

1.3V

PZH

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCTTHREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

TIED HIGH

and t

PLZ

OTHER

INPUTS

OR LOW

OUTPUT

DISABLE

PZL

IC WITH

THREE-

STATE

OUTPUT

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

6

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