Texas Instruments CD74HCT244M96, CD74HCT244M, CD74HCT244E, CD74HCT241M96, CD74HCT241E Datasheet

CD74HC240, CD74HCT240,
CD74HC241, CD74HCT241,

[ /Title
(CD74
HC240
,
CD74
HCT24
0,
CD74
HC241
,
CD74
HCT24
1,
CD74
HC244
,
CD74

Data sheet acquired from Harris Semiconductor
SCHS167

November 1997

Features

• CD74HC/HCT240 Inverting

• CD74HC/HCT241 Non-Inverting

• CD74HC/HCT244 Non-Inverting

• Typical Propagation Delay = 8ns at V
C

= 15pF, TA = 25oC for HC240

L

• Three-State Outputs

• Buffered Inputs

• High-Current Bus Driver Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

≤ 1µA at VOL, V

l

CC

= 5V,

o

CD74HC244, CD74HCT244

High Speed CMOS Logic

Octal Buffer/Line Drivers, Three-State

C to 125oC

CC

OH

Pinout

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241,

CD74HC244, CD74HCT244

(PDIP, SOIC)

TOP VIEW

241
244240

1

1OE

1OE

1A0

1A0
2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

2Y3
1A1
2Y2
1A2
2Y1
1A3
2Y0

GND

2
3
4
5
6
7
8
9

10

241
244 240

V

20

CC

2OE (241)

19

1Y0

18

2A3

17

1Y1

16

2A2

15

1Y2

14

2A1

13
12

1Y3

11

2A0

V

CC

2OE (240, 244)
1Y0
2A3
1Y1
2A2
1Y2
2A1

1Y3
2A0

1

File Number 1656.1

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

Description

The Harris CD74HC240 and CD74HCT240 are inverting
three-state buffershaving two active-low output enables. The
Harris CD74HC241, CD74HCT241, CD74HC244 and
CD74HCT244 are non-inverting three-state buffersthat differ
only in that the 241 has one active-high and one active-low
output enable, and the 244 has two active-low output
enables. All three types have identical pinouts.

Ordering Information

TEMP. RANGE

PART NUMBER

(oC) PACKAGE

CD74HC240E -55 to 125 20 Ld PDIP E20.3
CD74HCT240E -55 to 125 20 Ld PDIP E20.3
CD74HC241E -55 to 125 20 Ld PDIP E20.3
CD74HCT241E -55 to 125 20 Ld PDIP E20.3
CD74HC244E -55 to 125 20 Ld PDIP E20.3

PKG.

NO.

Functional Diagram

Ordering Information

TEMP. RANGE

PART NUMBER

(oC) PACKAGE

CD74HCT244E -55 to 125 20 Ld PDIP E20.3
CD74HC240M -55 to 125 20 Ld SOIC M20.3
CD74HCT241M -55 to 125 20 Ld SOIC M20.3
CD74HCT240M -55 to 125 20 Ld SOIC M20.3
CD74HC244M -55 to 125 20 Ld SOIC M20.3
CD74HCT244M -55 to 125 20 Ld SOIC M20.3

NOTES:

1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.

PKG.

NO.

240

AND

244
1OE
2OE

1A0

1A1

1A2

1A3

2A0

2A1

2A2

2A3
241

1OE
2OE

241

AND

244

240

2

4

6

8

11

13

15

17

1

19

18

16

14

12

9

7

5

3

1Y0

1Y0

1Y1

1Y1

1Y2

1Y2

1Y3

1Y3

2Y0

2Y0

2Y1

2Y1

2Y2

2Y2

2Y3

2Y3

= 20

V

CC

GND = 10

2

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±70mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-6 4.5 3.98 - - 3.84 - 3.7 - V

-7.8 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
6 4.5 - - 0.26 - 0.33 - 0.4 V

7.8 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Three-State Leakage
Current

I

OZ

VIL or

V

IH

-6--±0.5 - ±0.5 - ±10 µA

(V)

V

CC

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

- - 4.5 to

5.5

V

IL

- - 4.5 to

5.5

V

OH

VIH or

V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

CMOS Loads
High Level Output

-6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads

Low Level Output
Voltage

V

OL

VIH or

V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

CMOS Loads
Low Level Output

6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

VCC to

I

0 5.5 - - ±0.1 - ±1-±1µA

GND

I

CC

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5
Input Pin: 1 Unit Load
(Note 4)

Three-State Leakage
Current

I

OZ

VIL or

V

IH

- 5.5 - - ±0.5 - ±5-±10 µA

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

CD74HCT240

nA0-A3 1.5

1OE 0.7
2OE 0.7

CD74HCT241

nA0-A3 0.7

1OE 0.7
2OE 1.5

CD74HCT244

nA0-A3 0.7

1OE 0.7
2OE 0.7

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

4

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

Switching Specifications C

PARAMETER SYMBOL

= 50pF, Input tr, tf= 6ns

L

TEST

CONDI-

TIONS

25oC -40oC TO 85oC -55oC TO 125oC

V

CC

(V)

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

HC TYPES
Propagation Delay t

Data to Outputs
HC240

PLH

, t

PHLCL

= 50pF

2 - - 100 - - 125 - - 150 ns

4.5 - - 20 - - 25 - - 30 ns
CL = 15pF 5 - 8 - - - ----ns
C

= 50pF 6 - - 17 - - 21 - - 26 ns

L

Data to Outputs
HC241

t

PLH

, t

PHLCL

= 50pF 2 - - 110 - - 140 - - 165 ns

4.5 - - 22 - - 28 - - 33 ns
CL = 15pF 5 - 9 - - - ----ns
C

= 50pF 6 - - 19 - - 24 - - 28 ns

L

Data to Outputs
HC244

t

PLH

, t

PHLCL

= 50pF 2 - - 110 - - 140 - - 165 ns

4.5 - - 22 - - 28 - - 33 ns
CL = 15pF 5 - 9 - - - ----ns
C

= 50pF 6 - - 19 - - 24 - - 28 ns

L

Output Enable and Disable
Time

t

THL

, t

TLHCL

= 50pF 2 - - 150 - - 190 - - 225 ns

4.5 - - 30 - - 38 - - 45 ns

5-12-------ns
6 - -26- -33- -38ns

Output Transition Time t

TLH

, t

THLCL

= 50pF 2 - - 60 - - 75 - - 90 ns

4.5 - - 12 - - 15 - - 18 ns

6 - -10- -13- -15ns
Input Capacitance C
Three-State Output

C

CL = 50pF - 10 - 10 - - 10 - - 10 pF

I

CL = 50pF - - - 20 - - 20 - - 20 pF

O

Capacitance
Power Dissipation Capacitance

C

PD

CL = 15pF

(Notes 5, 6)

HC240 5 - 38 - - - ----pF
HC241 5 - 34 - - - ----pF
HC244 5 - 46 - - - ----pF

HCT TYPES

Propagation Delay

Data to Outputs
HCT240

Data to Outputs
HCT241

Data to Outputs
HCT244

t

PHL, tPLHCL

t

PHL, tPLHCL

t

PHL, tPLHCL

= 50pF 4.5 - - 22 - - 28 - - 33 ns

CL = 15pF 5 - 9 - - - ----ns

= 50pF 4.5 - - 25 - - 31 - - 38 ns

CL = 15pF 5 - 10 - - - ----ns

= 50pF 4.5 - - 25 - - 31 - - 38 ns

CL = 15pF 5 - 10 - - - ----ns

5

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

Switching Specifications C

PARAMETER SYMBOL

Output Enable and Disable

= 50pF, Input tr, tf= 6ns (Continued)

L

TEST

t

TLH,tTHLCL

CONDI-

TIONS

= 50pF 4.5 - - 30 - - 38 - - 45 ns

V

CC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN TYP MAX MIN TYP MAX

Times
Output Transition Time t
Input Capacitance C
Power Dissipation Capacitance

THL

, t

TLHCL

I

C

PD

= 50pF 4.5 - - 12 - - 15 - - 18 ns

CL = 50pF - 10 - 10 - - 10 - - 10 pF

(Notes 5, 6))

HCT240 - 5 - 40 - - - ----pF
HCT241 - 5 - 38 - - - ----pF
HCT244 - 5 - 40 - - - ----pF

NOTES:

5. CPD is used to determine the dynamic power consumption, per channel.

6. PD = V

2

fi (CPD + CL) where fi = Input Frequency, fO = Output Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

= 6ns

tr = 6ns tf = 6ns

INPUT

90%
50%
10%

V

CC

GND

tr = 6ns

INPUT

2.7V

1.3V

0.3V

t

f

3V

GND

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

90%

50%

10%

t

TLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

6ns 6ns

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

50%

t

t

OUTPUTS
ENABLED

PLZ

PHZ

10%

90%

90%

10%

t

PZL

t

PZH

OUTPUTS

DISABLED

50%

50%

FIGURE 3. HC THREE-STATE PROPAGATION DELAY

WAVEFORM

V

CC

GND

OUTPUTS
ENABLED

t

INVERTING

OUTPUT

THL

t

PHL

t

PLH

1.3V

10%

90%

t

TLH

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

0.3

t

t

PZL

PZH

6ns

1.3V

1.3V
OUTPUTS

ENABLED

t

r

OUTPUT

DISABLE

OUTPUT LOW

TO OFF

OUTPUT HIGH

TO OFF

t

t

OUTPUTS
ENABLED

6ns t

PLZ

PHZ

10%

90%

f

2.7

1.3

OUTPUTS

DISABLED

FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM

3V

GND

6

CD74HC240, CD74HCT240, CD74HC241, CD74HCT241, CD74HC244, CD74HCT244

Test Circuits and Waveforms

OTHER

INPUTS

TIED HIGH

OR LOW

OUTPUT

DISABLE

NOTE: Open drain waveforms t
VCC, CL = 50pF.

FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

PLZ

and t

PZL

(Continued)

IC WITH

THREE-

STATE

OUTPUT

OUTPUT

= 1kΩ

R

L

C

L

50pF

VCC FOR t
GND FOR t

PLZ

PHZ

AND t

AND t

PZL

PZH

are the same as those for three-state shown on the left. The test circuit is Output RL=1kΩto

7

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