Data sheet acquired from Harris Semiconductor
/
j
/
SCHS165
September 1997
CD74HC195
High Speed CMOS Logic
4-Bit Parallel Access Register
[ /Title
(CD74
HC195
)
Sub-
ect
(High
Speed
CMOS
Logic
4-Bit
Parallel
Access
Register)
Autho
Features
• Asynchronous Master Reset
K, (D) Inputs to First Stage
•J,
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical f
C
= 15pF, TA = 25oC
L
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
V
CC
= 50MHz at VCC = 5V,
MAX
= 5V
o
C to 125oC
= 30%, NIH= 30%of VCCat
IL
Description
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
The two modes of operation, shift right (Q
load, are controlled by the state of the Parallel Enable (
input. Serial data enters the first flip-flop (Q
inputs when the
direction Q
transition. The J and K inputs provide the flexibility of the JKtype input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the
tion, data on the parallel inputs (D0-D3) is transferred to the
respective Q
be achieved by tying the Q
holding the
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The CD74HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J,
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (
independent of any other input condition.
PE input is high, and is shifted one bit in the
0-Q1-Q2-Q3
PE input is Low. After the Low to High clock transi-
0-Q3
PE input low.
K, Pn and PE inputs for logic operations, other
following each Low to High clock
outputs. Shift left operation (Q3-Q2) can
outputs to the Dn-1 inputs and
n
MR) input sets all Q outputs Low,
) and parallel
0-Q1
) via the J and K
0
PE)
PInout
MR
D0
D1
D2
D3
GND
1
2
J
3
K
4
5
6
7
8
CD74HC195
(PDIP, SOIC)
TOP VIEW
Ordering Information
PKG.
PART NUMBER TEMP. RANGE (oC) PACKAGE
CD74HC195E -55 to 125 16 Ld PDIP E16.3
16
V
CC
15
Q
0
14
Q
1
13
Q
2
12
Q
3
11
Q
3
10
CP
9
PE
CD74HC195M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number.
2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.
NO.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1997
1
File Number 1482.1
Functional Diagram
CP
MR
CD74HC195
D0D1D2D
PE
94567
2
J
10
3
K
1
15 14 13 12
3
11
Q
3
Q0Q1Q2Q
3
TRUTH TABLE
INPUTS OUTPUT
OPERATING MODES
MR CP PE J KDnQ0Q
Q
1
Q
2
Q
3
3
Asynchronous Reset L XXXXXLLLLH
Shift, Set First Stage H ↑ hhhX
H
Shift, Reset First Stage H ↑ hllXLq0q
Shift, Toggle First Stage H ↑ hhlXq
0
Shift, Retain First Stage H ↑ hlhXq0q
Parallel Load H ↑ lXXdnd0d
q
0
q
0
0
1
q
1
1
q
1
q
1
d
2
q
2
q
2
q
2
q
2
q
q
q
q
d3 d2
2
2
2
2
NOTE: H = High Voltage Level
L = Low Voltage Level,
X = Don’t Care
↑ = Transition from Low to High Level
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition
h = Low Voltage Level One Set-up Time prior to the High to Low Clock Transition,
dn (qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low to High Clock
Transition.
2
CD74HC195
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
CC
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CC
DC Electrical Specifications
TEST
CONDITIONS
PARAMETER SYMBOL
High Level Input
Voltage
Low Level Input
Voltage
High Level Output
Voltage
V
IH
V
IL
V
OH
CMOS Loads
High Level Output
Voltage
TTL Loads
Low Level Output
Voltage
V
OL
CMOS Loads
Low Level Output
Voltage
TTL Loads
Input Leakage
Current
Quiescent Device
I
CC
I
I
Current (Note)
NOTE: For dual-supply systems theorectical worst case (V
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
I
- - 2 1.5 - - 1.5 - 1.5 - V
- - 2 - - 0.5 - 0.5 - 0.5 V
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
VCC or
-6--±0.1 - ±1-±1 µA
GND
VCC or
0 6 - - 8 - 80 - 160 µA
GND
o
25
C -40oC TO 85oC -55oC TO 125oC
(V)
V
CC
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
= 2.4V, VCC = 5.5V) specification is 1.8mA.
I
UNITSV
3
Prerequisite For Switching Function
PARAMETER SYMBOL
Clock Frequency f
MR Pulse Width t
Clock Pulse Width t
Set-up Time
J, K, PE to Clock
Hold Time
J, K, PE to Clock
Removal Time,
MR to Clock
MAX
t
t
REM
SU
t
w
w
H
CD74HC195
TEST
CONDITIONS VCC (V)
- 26-5-4-MHz
4.5 30 - 25 - 20 - MHz
6 35 - 29 - 23 - MHz
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
- 2 100 - 125 - 150 - ns
4.5 20 - 25 - 30 - ns
617-21-26-ns
- 23-3-3-ns
4.53-3-3-ns
65-3-3-ns
- 2 80 - 100 - 120 - ns
4.5 16 - 20 - 24 - ns
614-17-20-ns
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN MAX MIN MAX MIN MAX
Switching Specifications Input t
, tf = 6ns
r
TEST
PARAMETER SYMBOL
CONDITIONS VCC (V)
HC TYPES
Propagation Delay, CP to
Output
t
PLH
, t
PHLCL
= 50pF 2 - 175 220 265 ns
4.5 - 35 44 53 ns
6 - 30 37 45 ns
Propagation Delay,
MR toOutput
t
PLH
, t
PHLCL
= 50pF 2 - 150 190 225 ns
4.5 - 30 38 45 ns
6 - 26 33 38 ns
Output Transition Times
(Figure 1)
t
TLH
, t
THLCL
= 50pF 2 - 75 95 110 ns
4.5 - 15 19 22 ns
6 - 13 16 19 ns
Input Capacitance C
CP to Qn Propagation Delay t
MR to Q
n
PLH
Maximum Clock Frequency f
Power Dissipation
IN
, t
PHLCL
t
PHL
MAX
C
PD
---1010 10pF
= 15pF 5 14 - - - ns
CL= 15pF 5 13 - - - ns
CL= 15pF 5 50 - - - MHz
CL= 15pF 45 - - - pF
Capacitance (Notes 4, 5)
NOTES:
4. CPD is used to determine the dynamic power consumption, per flip-flop.
5. PD=V
CC
2
fi+∑ (CLV
2
+fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC= Supply Voltage.
CC
25oC -40oC TO 85oC -55oC TO 125oC
UNITSTYP MAX MAX MAX
4
Test Circuit and Waveforms
CLOCK
Q OR
t
r
90%
V
S
10%
t
W
t
PLHtPHL
Q
90%
10%
l/f
t
TLH
MAX
t
t
f
THL
0.5 V
V
CC
GND
CC
CD74HC195
RESET
CLOCK
Q
t
PHL
Q
t
W
V
S
t
PLH
0.5 V
CC
V
S
t
REM
0.5 V
CC
V
CC
GND
V
CC
GND
FIGURE 1. CLOCK PRE-REQUISITE AND PROPAGATION
DELAYS AND OUTPUT TRANSITION TIMES
PE, K
J
t
SU
CLOCK
FIGURE 3. J, K OR PARALLEL ENABLE PRE-REQUISITE TIMES
FIGURE 2. MASTER RESET PRE-REQUISITE AND
PROPAGATION DELAYS
VALID
V
V
S
t
h
0.5 V
CC
CC
GND
GND
5
IMPORTANT NOTICE
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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright 1998, Texas Instruments Incorporated
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