Texas Instruments CD74HCT194E, CD74HC194M96, CD74HC194M, CD74HC194E, CD54HC194F3A Datasheet

CD74HC194,

/
j

[ /Title
(CD74
HC194,
CD74H
CT194)

Sub-

ect
(High­Speed
CMOS
Logic
4-Bit

Data sheet acquired from Harris Semiconductor
SCHS164

September 1997

Features

• Four Operating Modes

- Shift Right, Shift Left, Hold and Reset

• Synchronous Parallel or Serial Operation

• Typical f
T

= 25oC

A

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

CD74HCT194

High-Speed CMOS Logic

4-Bit Bidirectional Universal Shift Register

Description

The Harris CD74HC194 and CD74HCT194 are 4-bit shift

C to 125oC

CC

OH

registers with Asynchronous Master Reset (
allel mode (S0 and S1 are high), data is loaded into the
associated flip-flop and appears at the output after the posi­tive transition of the clock input (CP). During parallel loading
serial data flow is inhibited. Shift left and shift right are
accomplished synchronously on the positive clock edge with
serial data entered at the shift left (DSL) serial input for the
shift right mode, and at the shift right (DSR) serial input for
the shift left mode. Clearing the register is accomplished by
a Low applied to the Master Reset (

MR) pin.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC194E -55 to 125 16 Ld PDIP E16.3
CD74HCT194E -55 to 125 16 Ld PDIP E16.3
CD74HC194M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die for this part number is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

MR). In the par-

PKG.

NO.

Pinout

CD74HC194, CD74HCT194

(PDIP, SOIC)

TOP VIEW

V

1

MR

2

DSR

3

D

0

4

D

1

5

D

2

6

D

3

DSL

7
8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

16

CC

15

Q

0

14

Q

1

13

Q

2

12

Q

3

11

CP

10

S1

9

S0

File Number 1668.1

Functional Diagram

CD74HC194, CD74HCT194

D

D

D

D

DSL

DSR

S0
S1

MR

CP

3

0

4

1

5

2

6

3

2 9 10 1 11

7

15

14

13

12

GND = 8

= 16

V

CC

Q

0

Q

1

Q

2

Q

3

TRUTH TABLE

INPUTS OUTPUT

OPERATING

MODE

CP MR S1 S0 DSR DSL D

n

Q

Q

0

Q

1

Q

2

3

Reset (Clear) X L X X X X X LLLL
Hold (Do Nothing) X H l (Note 2) l (Note 2) X X X q
Shift Left ↑ H h l (Note 2) X l X q

↑ H h l (Note 2) X h X q

0

1

1

Shift Right ↑ H l (Note 2) h l X X L q

↑ H l (Note 2) h h X X H q

Parallel Load ↑ Hh hXXdnd

0

q

1

q

2

q

2

0

0

d

1

q

2

q

3

q

3

q

1

q

1

q

2

q

3

L

H

q

2

q

2

d

3

NOTES:

1. H = High VoltageLevel,
h = High Voltage Level One Set-up Time Prior To The Low to High Clock Transition,
L = Low Voltage Level,
l = Low Voltage Level One Set-up Time Prior to the Low to High Clock Transition,
dn(qn) = Lower Case Letters Indicate the State of the Referenced Input (or output) One Set-up Time Prior to the Low To High Clock
Transition,
X = Don’t Care,
↑ = Transition from Low to High Level

2. The High to Low transition of the S0 and S1 Inputs on the CD74HC194, CD74HCT194 should only take place while CP is High for
Conventional Operation.

2

CD74HC194, CD74HCT194

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 190

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

V

IH

V

IL

V

OH

V

OL

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

Low Level Output
Voltage
TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

3