Texas Instruments CD74HCT173E, CD74HCT173M96, CD74HCT173M, CD74HC173M96, CD74HC173M Datasheet
...
CD74HC173,
/
[ /Title
(CD74H
C173,
CD74H
CT173)
Subject
(High
Speed
CMOS
Logic
Quad DType
Data sheet acquired from Harris Semiconductor
SCHS158
February 1998
Features
• Three-State Buffered Outputs
• Gated Input and Output Enables
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
at VCC = 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
= 0.8V (Max), VIH = 2V (Min)
IL
- CMOS Input Compatibility, I
= 30%, NIH = 30% of V
IL
≤ 1µA at VOL, V
l
o
Pinout
CD74HC173, CD74HC173
(PDIP, SOIC)
TOP VIEW
C to 125oC
CC
OH
CD74HCT173
High Speed CMOS Logic
Quad D-Type Flip-Flop, Three-State
Description
The Harris CD74HC173 and CD74HCT173 high speed
three-state quad D-type flip-flops are fabricated with silicon
gate CMOS technology. They possess the low power consumption of standard CMOS Integrated circuits, and can
operate at speeds comparable to the equivalent low power
Schottky devices. The buffered outputs can drive 15 LSTTL
loads. The large output drive capability and three-state feature make these parts ideally suited for interfacing with bus
lines in bus oriented systems.
The four D-typeflip-flops operate synchronously from a common clock. The outputs are in the three-state mode when
either of the two output disable pins are at the logic “1” level.
The input ENABLES allow the flip-flops to remain in their
present states without having to disrupt the clock If either of
the 2 input ENABLES are taken to a logic “1” level, the Q
outputs are fed back to the inputs, forcing the flip-flops to
remain in the same state. Reset is enabled by taking the
MASTER RESET (MR) input to a logic “1” level. The data
outputs change state on the positive going edge of the clock.
The CD74HCT173 logic family is functionally, as well as pin
compatible with the standard 74LS logic family
Ordering Information
TEMP.RANGE
PART NUMBER
(oC) PACKAGE
.
PKG.
NO.
OE
OE2
Q
Q
Q
Q
CP
GND
V
1
2
3
0
4
1
5
2
6
3
7
8
16
CC
MR
15
14
D0
13
D1
D2
12
D3
11
E2
10
9
E1
CD74HC173E -55 to 125 16 Ld PDIP E16.3
CD74HCT173E -55 to 125 16 Ld PDIP E16.3
CD74HC173M -55 to 125 16 Ld SOIC M16.15
CD74HCT173M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number.Add the suffix 96 to
obtain the variant in the tape and reel.
2. Wafer and die for this part number is available which meets all
electrical specifications. Please contact your local sales office or
Harris customer service for ordering information.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© Harris Corporation 1998
1
File Number 1641.1
Functional Diagram
E1
E2
14
D0
13
D1
12
D2
11
D3
7
CP
MR
OE1
OE2
TRUTH TABLE
INPUTS
CD74HC173, CD74HCT173
10
9
3
Q
0
4
Q
1
5
Q
2
6
Q
3
2
115
DATA OUTPUT
n
MR CP
DATA ENABLE
E1 E2 D Q
HXXXXL
LLXXXQ
L↑HXXQ
L↑XHXQ
0
0
0
L↑LLLL
L↑LLHH
NOTE:
When either OE1 or OE2 (or both) is (are) high the output isdisabled
to the high-impedance state, however, sequential operation of the
flip-flops is not affected.
H = High Voltage Level
L = Low Voltage Level
X = Irrelevant
↑ = Transition from Low to High Level
Q0= Level Before the Indicated Steady-State Input Conditions Were
Established
2
Logic Diagram
9
E1
10
E2
14
D0
7
CP
15
MR
1
OE1
2
OE2
CD74HC173, CD74HCT173
DQ
CP Q
R
V
CC
P
3
Q
0
N
D1
D2
D3
13
12
11
3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT
IN DASHED ENCLOSURE
4
Q
1
5
Q
2
6
Q
3
3
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