Texas Instruments CD74HCT166M96, CD74HCT166M, CD74HCT166E, CD74HC166M96, CD74HC166M Datasheet

CD74HC166,

/
j

[ /Title
(CD74
HC166
,
CD74
HCT16

6)
Sub­ect

(High
Speed
CMOS
Logic
8-Bit
Paral­lel­In/Seri

Data sheet acquired from Harris Semiconductor
SCHS157

February 1998

Features

• Buffered Inputs

• Typical f

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

Pinout

= 50MHz at VCC = 5V, CL = 15pF, TA = 25oC

MAX

o

= 30%, NIH = 30% of V

IL

CD74HC166, CD74HCT166 (PDIP, SOIC)

GND

C to 125oC

CC

TOP VIEW

1

DS

2

D0
D1

3

D2

4

D3

5
6

CE

7

CP

8

CD74HCT166

High Speed CMOS Logic

8-Bit Parallel-In/Serial-Out Shift Register

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

Ordering Information

TEMP. RANGE

PART NUMBER

CD74HC166E -55 to 125 16 Ld PDIP E16.3
CD74HCT166E -55 to 125 16 Ld PDIP E16.3
CD74HC166M -55 to 125 16 Ld SOIC M16.15
CD74HCT166M -55 to 125 16 Ld SOIC M16.15
CD54HC166W -55 to 125 Wafer

NOTES:

1. When ordering,use the entire partnumber.Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

V

16

CC

15

PE

14

D7

13

Q7
D6

12

D5

11

D4

10

9

MR

(oC) PACKAGE

≤ 1µA at VOL, V

l

OH

PKG.

NO.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1501.1

Functional Diagram

CD74HC166, CD74HCT166

D0 D1 D2 D3 D4 D5 D6 D7

PE

D

CP
CE

MR

S

P ARALLEL ENABLE CIRCUIT

D0 D7

8 - REGISTERS

Q7

TRUTH TABLE

INPUTS

INTERNAL

MASTER

RESET

PARALLEL

ENABLE

CLOCK

ENABLE CLOCK SERIAL

PARALLEL

D0 D7 Q0 Q1

Q STATES

OUTPUT

Q7

LXXXXXLLL
H X L L X X Q00 Q10 Q0
HLL↑ X a...h a b h
HHL ↑ H X H Q0n Q6n
HHL ↑ L X L Q0n Q6n
HXH↑ X X Q00 Q10 Q70

NOTES:
H = High Voltage Level
L = Low Voltage Level
X = Don’t Care
↑ = Transition from Low to High Level
a...h = The level of steady-state input at inputs D0 thru D7, respectively.
Q00, Q10, Q70 = The level of Q0, Q1, or Q7, respectively, before the indicated steady-state input conditions were established.
Q0n, Q6n = The level of Q0 or Q6, respectively, before the most recent ↑ transition of the clock.

2

CD74HC166, CD74HCT166

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current, per Output, I

O

For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

3

CD74HC166, CD74HCT166

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

I

CC

V

V

V

V

I

CC

∆I

IH

IL

OH

OL

I

I

CC

VCC or

GND

- - 4.5 to

- - 4.5 to

VIH or

V

VIH or

V

VCC to

GND

VCC or

GND

V

CC

-2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

IL

VCC (V)

0 6 - - 8 - 80 - 160 µA

5.5

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

DS, D0-D7 0.2

PE 0.35

CP, CE 0.5

MR 0.2

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g., 360µA max at 25oC.

Prerequisite For Switching Specifications

PARAMETER SYMBOL VCC (V)

HC TYPES

Clock Frequency
(Figure 1)

f

MAX

26-5-4-MHz

4.5 30 - 25 - 20 - MHz
6 35 - 29 - 23 - MHz

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

4

CD74HC166, CD74HCT166

Prerequisite For Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

MR Pulse Width
(Figure 1)

Clock Pulse Width
(Figure 1)

Set-up Time
Data and CE to Clock
(Figure 5)

Hold Time
Data to Clock
(Figure 5)

Removal Time
MR to Clock
(Figure 5)

Set-up Time
PE to CP
(Figure 5)

Hold Time
PE to CP or CE
(Figure 5)

HCT TYPES

Clock Frequency (Figure 2) f
MR Pulse Width (Figure 2) t
Clock Pulse Width (Figure 2) t
Set-up Time Data and CE to

Clock (Figure 6)
Hold Time Data to Clock

(Figure 6)
Removal Time MR to Clock

(Figure 6)
Set-up Time PE to CP (Figure 6) t
Hold Time PE to CP or CE

(Figure 6)

t

t

t

REM

t

MAX

t

t

REM

t

W

SU

t

SU

t

SU

t

SU

t

w

2 100 - 125 - 150 - ns

4.5 20 - 25 - 30 - ns
617-21-26-ns
2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns
2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

H

21-1-1-ns

4.51-1-1-ns
61-1-1-ns
20-0-0-ns

4.50-0-0-ns
60-0-0-ns
2 145 - 180 - 220 - ns

4.5 29 - 36 - 44 - ns
625-31-38-ns

H

20-0-0-ns

4.50-0-0-ns
60-0-0-ns

4.5 25 - 20 - 16 - MHz

w
w

4.5 35 - 44 - 53 - ns

4.5 20 - 25 - 30 - ns

4.5 16 - 20 - 24 - ns

H

4.50-0-0-ns

4.50-0-0-ns

4.5 30 - 38 - 45 - ns

H

4.50-0-0-ns

UNITSMIN MAX MIN MAX MIN MAX

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay,
Clock to Output (Figure 3)

t

PLH

, t

, tf = 6ns

r

TEST

25oC -40oC TO 85oC -55oC TO 125oC

CONDITIONS VCC (V)

PHLCL

= 50pF 2 - 160 200 240 ns

4.5 - 32 40 48 ns
CL= 15pF 5 13 - - - ns
CL = 50pF 6 - 27 34 41 ns

5

UNITSTYP MAX MAX MAX

CD74HC166, CD74HCT166

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Output Transition Time
(Figure 3)

t

TLH

, t

CONDITIONS VCC (V)

THLCL

= 50pF 2 - 75 95 110 ns

4.5 - 15 19 22 ns

6 - 13 16 19 ns

Propagation Delay
MR to Output
(Figure 3)

t

PHL

CL= 50pF 2 - 160 200 240 ns

4.5 - 32 40 48 ns

6 - 27 34 41 ns
Input Capacitance C
Power Dissipation

C

I

PD

---1010 10pF

- 5 41 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay,

t

PLH

, t

PHLCL

= 50pF 4.5 - 40 50 60 ns
Clock to Output
(Figure 4)

Output Transition Time

t

TLH

, t

THLCL

= 50pF 4.5 - 15 19 22 ns
(Figure 4)

Propagation Delay

t

PHL

CL= 50pF 4.5 - 40 50 60 ns

MR to Output (Figure 4)
Input Capacitance C

I

---1010 10pF

NOTES:

5. CPD is used to determine the dynamic power consumption, per gate.

6. PD=CPDV

2

fi+ ∑ (CLV

CC

2

+fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC= Supply

CC

Voltage.

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

Test Circuits and Waveforms

trC

L

CLOCK

10%

90%

50%

10%

tfC

t

L

WL

tWL+ tWH=

50%

t

WH

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

I

f

CL

50%

V

CC

GND

1.3V

I

fC

L

3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

t

fCL

t

WL

= 6ns

1.3V

t

WH

t

WL

+ tWH=

NOTE: Outputs should be switching from 10% VCC to 90% VCC in
accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALLTIMES AND

PULSE WIDTH

6

CD74HC166, CD74HCT166

Test Circuits and Waveforms

(Continued)

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

90%
50%
10%

THL

90%

t

PLH

50%

10%

INVERTING

OUTPUT

t

PHL

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

tfC

L

V

50%

GND

t

H(L)

V
50%

t

SU(L)

GND

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

90%

10%

t

H(H)

CC

CC

= 6ns

tr = 6ns

INPUT

t

2.7V

1.3V

0.3V

THL

t

f

3V

GND

t

TLH

90%

t

PLH

1.3V

10%

INVERTING

OUTPUT

t

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CLOCK

INPUT

DAT A

INPUT

t

SU(H)

trC

L

2.7V

0.3V

t

H(H)

1.3V

1.3V

tfC

L

1.3V

t

H(L)

1.3V

t

SU(L)

3V

GND

3V

GND

OUTPUT

t

REM

V

CC

SET, RESET
OR PRESET

50%

90%

t

PLH

IC

t

TLH

t

THL

90%

50%

10%
t

PHL

GND

C

L

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVALTIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

OUTPUT

t

REM

3V
SET, RESET
OR PRESET

1.3V

90%

1.3V
t

IC

t

PLH

TLH

t

THL

90%

1.3V
10%

t

PHL

GND

C

L

50pF

FIGURE 6. HCT SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS

7

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