Texas Instruments CD74HCT165M96, CD74HCT165M, CD74HCT165E, CD74HC165M96, CD74HC165M Datasheet

CD74HC165,

/

[ /Title
(CD74H
C165,
CD74H
CT165)

Subject
(High
Speed
CMOS
Logic 8­Bit Par­allel-

Data sheet acquired from Harris Semiconductor
SCHS156

February 1998

Features

• Buffered Inputs

• Asynchronous Parallel Load

• Complementary Outputs

• Typical f
T

= 25oC

A

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 60MHz at VCC = 5V, CL = 15pF,

MAX

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

o

CD74HCT165

High Speed CMOS Logic

8-Bit Parallel-In/Serial-Out Shift Register

C to 125oC

CC

OH

Pinout

CD74HC165, CD74HCT165

(PDIP, SOIC)

TOP VIEW

16

1

PL

2

CP

3

D4

4

D5

5

D6

6

D7

7

Q

7

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

V

CC

15

CE

14

D3

13

D2

12

D1
D0

11
10

DS

9

Q

7

1

File Number 1672.1

CD74HC165, CD74HCT165

Description

The Harris CD74HC165 and CD74HCT165 are 8-bit parallel
or serial-in shift registers with complementary serial outputs
(Q

and Q7) available from the last stage. When the parallel

7

load (

PL) input is LOW, parallel data from the D0 to D7
inputs are loaded into the register asynchronously. When the
PL is HIGH, data enters the register serially at the DS input
and shifts one place to the right (Q

0→Q1→Q2

, etc.) with
each positive-going clock transition. This feature allow paral­lel-to-serial converter expansion by typing the Q

output to

7

the DS input of the succeeding device.
For predictable operation the LOW-to-HIGH transition of

should only take place while CP is HIGH. Also, CP an d

CE
CE

should be LOW before the LOW-to-HIGH transition of PL to

Functional Diagram

11

D0

12

D1

13

D2

PARALLEL

DAT A

INPUTS

D3
D4
D5
D6
D7
DS

14

3

4
5
6

10

prevent shifting the data when

PL goes HIGH.

Ordering Information

TEMP.RANGE

PART NUMBER

CD74HC165E -55 to 125 16 Ld PDIP E16.3
CD74HCT165E -55 to 125 16 Ld PDIP E16.3
CD74HC165M -55 to 125 16 Ld SOIC M16.15
CD74HCT165M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die is available which meets all electrical
specifications. Please contact your local sales office or Harris
customer service for ordering information.

9

Q

7

SERIAL

7

OUTPUTS

Q

7

(oC) PACKAGE PKG. NO.

151

PL

CE

CP

2

GND = 8
VCC = 16

TRUTH TABLE

INPUTS Qn REGISTER OUTPUTS

OPERATING MODE

PL CE CP DS D0 - D7 Q

Q1 - Q

0

Q

6

7

Parallel Load L X X X L L L-L L H

LXXXHHH-HHL

Serial Shift H L ↑ lXLq

HL↑ hXHq

Hold Do Nothing H H X X X q

0

0 -q5

0 -q5

q

1 -q6

q

6

q

6

q

7

Q

7

q

6

q

6

q

7

2

CD74HC165, CD74HCT165

TRUTH TABLE

INPUTS Qn REGISTER OUTPUTS

OPERATING MODE

NOTE:
H = High Voltage Level
h = High Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
l = Low Voltage Level One Set-up Time Prior To The Low-to-high Clock Transition
L = Low Voltage Level
X = Don’t Care
↑ = Transition from Low to High Level
qn= Lower Case Letters Indicate The State Of the Reference Output Clock Transition

PL CE CP DS D0 - D7 Q

Q1 - Q

0

Q

6

7

Q

7

3

CD74HC165, CD74HCT165

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Drain Current per Output, IO

For VO < -0.5V VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±25mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

25oC -40oC TO 85oC -55oC TO 125oC

VCC (V)

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIH or

V

-0.02 2 1.9 - - 1.9 - 1.9 - V

IL

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIH or

V

0.02 2 - - 0.1 - 0.1 - 0.1 V

IL

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

4

CD74HC165, CD74HCT165

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

I

CC

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

∆I

CC

(Note 4)

VCC or

GND

- - 4.5 to

- - 4.5 to

VIH or

V

VIH or

V

VCC to

GND

VCC or

GND

V

-2.1

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

IL

IL

CC

VCC (V)

0 6 - - 8 - 80 - 160 µA

5.5

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2-- 2 - 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

DS, D0 to D7 0.35

CP, PL 0.65

NOTE: Unit Load is ∆ICClimit specified in DC Electrical
Specifications table, e.g. 360µA max at 25oC.

Prerequisite For Switching Specifications

PARAMETER SYMBOL VCC (V)

HC TYPES

CP Pulse Width t

WL,tWH

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN MAX MIN MAX MIN MAX

5

CD74HC165, CD74HCT165

Prerequisite For Switching Specifications (Continued)

25oC -40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

UNITSMIN MAX MIN MAX MIN MAX

PL Pulse Width t

WL

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

Set-up Time t

SU

2 80 - 100 - 120 - ns

DS to CP 4.5 16 - 20 - 24 - ns

614-17-20-ns

CE to CP t

SU(L)

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

D0-D7 to PL t

SU

2 80 - 100 - 120 - ns

4.5 16 - 20 - 24 - ns
614-17-20-ns

Hold Time t

H

235-45-55-ns

DS to CP or CE 4.5 7 - 9 - 11 - ns

66-8-9-ns

CE to CP t

H

20-0-0-ns

4.50-0-0-ns
60-0-0-ns

Recovery Time t

REC

2 100 - 125 - 150 - ns

PL to CP 4.5 20 - 25 - 30 - ns

617-21-26-ns

Maximum Clock Pulse
Frequency

f

MAX

26-5-4-MHz

4.5 30 - 24 - 20 - MHz
6 35 - 28 - 24 - MHz

HCT TYPES

CP Pulse Width tWL, t
PL Pulse Width t
Set-up Time

WL

t

WH

SU

4.5 18 - 23 - 27 - ns

4.5 20 - 25 - 30 - ns

4.5 20 - 25 - 30 - ns

DS to CP
CE to CP t
D0-D7 to PL t

Hold Time

SU(L)

SU

t

H

4.5 20 - 25 - 30 - ns
620-25-30-ns

4.5 7 - 9 - 11 - ns

DS to CP or CE
CE to CP tS,t

Recovery Time

t

REC

H

4.50-0-0-ns

4.5 20 - 25 - 30 - ns

PL to CP

Maximum Clock Pulse

f

MAX

4.5 27 - 22 - 18 - MHz

Frequency

6

CD74HC165, CD74HCT165

Switching Specifications Input t

, tf = 6ns

r

TEST

PARAMETER SYMBOL

CONDITIONS VCC (V)

HC TYPES

Propagation Delay t

CP or CE to Q7 or Q

7

PLH

, t

PHLCL

= 50pF 2 - 165 205 250 ns

4.5 - 33 41 50 ns
CL= 15pF 5 13 - - - ns
CL= 50pF 6 - 28 35 43 ns

PL to Q7 or Q

7

t

PLH

, t

PHLCL

= 50pF 2 - 175 220 265 ns

4.5 - 35 44 53 ns
CL= 15pF 5 14 - - - ns
CL= 50pF 6 - 30 37 45 ns

D7 to Q7 or Q

7

t

PLH

, t

PHLCL

= 50pF 2 - 150 190 225 ns

4.5 - 30 38 45 ns
CL= 15pF 5 12 - - - ns
CL= 50pF 6 - 26 33 38 ns

Output Transition Times t

TLH

, t

THLCL

= 50pF 2 - 75 95 110 ns

4.5 - 15 19 22 ns

6 - 13 16 19 ns
Input Capacitance C
Power Dissipation

IN

C

PD

---1010 10pF

- 5 17 - - - pF
Capacitance
(Notes 5, 6)

HCT TYPES

Propagation Delay t

CP or CE to Q7 or Q
PL to Q7 or Q

7

7

PLH

t

PLH

, t

PHLCL

, t

PHLCL

= 50pF 4.5 - 40 50 60 ns

CL= 15pF 5 17 - - - ns

= 50pF 4.5 - 40 50 60 ns

CL= 15pF 5 17 - - - ns

D7 to Q7 or Q

7

t

PLH

, t

PHLCL

= 50pF 4.5 - 35 44 53 ns

CL= 15pF 5 14 - - - ns
Output Transition Times t
Input Capacitance C
Power Dissipation

TLH

, t

THLCL

IN

C

PD

= 50pF 4.5 - 15 19 22 ns

CL= 50pF - - 10 10 10 pF

- 5 24 - - pF
Capacitance
(Notes 5, 6)

NOTES:

5. CPD is used to determine the dynamic power consumption, per package.

6. PD=V

CC

2

fi+ ∑ (CLV

2

+fO) where fi= Input Frequency, fO= Output Frequency, CL= Output Load Capacitance, VCC= Supply

CC

Voltage.

25oC -40oC TO 85oC -55oC TO 125oC

UNITSTYP MAX MAX MAX

7

Test Circuits and Waveforms

CP OR CE

Q7 OR Q

INPUT D7

Q7 OR Q

t

TLH

t

r

90%

10%

t

W

1/f

t

PHL

90%

7

10%

MAX

t

PLH

t

f

V

S

GND

V

S

t

THL

Q7OR Q

PL

7

t

W

V

S

t

PHL

FIGURE 3. SERIAL-SHIFT MODE FIGURE 4. PARALLEL-LOAD MODE

7

t

PLH

t

r

90%

10%

90%

10%

t

THL

t

f

t

PHL

V

S

t

TLH

INPUT LEVEL

GND

INPUTS D0-D7

PL

VALID

V

S

t

SU

t

H

V

S

FIGURE 5. PARALLEL-LOAD MODE FIGURE 6. PARALLEL-LOAD MODE

t

PLH

V

S

INPUT LEVEL

INPUT LEVEL

GND

INPUT LEVEL

GND

INPUTS DS

CP OR

CE

VALID

t

SU

t

H

INPUT LEVEL

GND
INPUT LEVEL

GND

PL

CP OR CE

V

t

REC

S

INPUT LEVEL

V

S

FIGURE 7. SERIAL-SHIFT MODE FIGURE 8. SERIAL-SHIFT MODE

CE INHIBITED

INPUT LEVEL

CP

CE

t

t

SU

SU

(L) t

SU

CP

t

INHIBITED

SU

GND

(L)

INPUT LEVEL
GND

FIGURE 9. SERIAL-SHIFT, CLOCK-INHIBIT MODE

GND
INPUT LEVEL

GND

8

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