Texas Instruments CD74HCT157E, CD74HCT158E, CD74HCT157M96, CD74HCT157M, CD74HC158M Datasheet

...
1
Data sheet acquired from Harris Semiconductor SCHS153
Features
• Common Select Inputs
• Separate Enable Inputs
• Buffered inputs and Outputs
• Fanout (Over Temperature Range)
• Wide Operating Temperature Range . . . -55
o
C to 125oC
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL Logic ICs
• HC Types
- 2V to 6V Operation
- High NoiseImmunity: N
IL
= 30%, NIH= 30%of VCCat
V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), VIH = 2V (Min)
- CMOS Input Compatibility, I
l
1µA at VOL, V
OH
Pinout
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
(PDIP, SOIC)
TOP VIEW
14
15
16
9
13 12 11 10
1 2 3 4 5
7
6
8
S
1I
0
1I
1
1Y
2I
0
2I
1
GND
2Y
V
CC
4I
0
4I
1
4Y 3I
0
3I
1
3Y
E
September 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright
© Harris Corporation 1997
File Number 1642.2
CD74HC157, CD74HCT157,
CD74HC158, CD74HCT158
High Speed CMOS Logic
Quad 2-Input Multiplexers
[ /Title (CD74H C157, CD74H CT157, CD74H C158, CD74H CT158) /
Subject (High Speed
2
Description
The Harris CD74HC157, CD74HCT157, CD74HC158 and CD74HCT158 are quad 2-input multiplexers which select four bits of data from two sources under the control of a common Select input (S). The Enable input (
E) is active Low.
When (
E) is High, all of the outputs in the 158, the inverting
type, (
1Y-4Y) are forced High and in the 157, the non-
inverting type, all of the outputs (
1Y-4Y) are forced Low,
regardless of all other input conditions. Moving data from two groups of registers to four common
output busses is a common use of these devices. The state of the Select input determines the particular register from which the data comes. They can also be used as function generators.
Ordering Information
PART NUMBER TEMP. RANGE (oC) PACKAGE
PKG.
NO.
CD74HC157E -55 to 125 16 Ld PDIP E16.3 CD74HCT157E -55 to 125 16 Ld PDIP E16.3 CD74HC158E -55 to 125 16 Ld PDIP E16.3 CD74HCT158E -55 to 125 16 Ld PDIP E16.3 CD74HC157M -55 to 125 16 Ld SOIC M16.15 CD74HCT157M -55 to 125 16 Ld SOIC M16.15 CD74HC158M -55 to 125 16 Ld SOIC M16.15
NOTES:
1. When ordering, use the entire part number. Add the suffix 96 to obtain the variant in the tape and reel.
2. Wafer ordiefor this partnumberis available whichmeets all elec­trical specifications. Please contact your local sales office or Harris customer service for ordering information.
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
3
Functional Diagram
TRUTH TABLE
ENABLE
SELECT
INPUT DATA INPUTS
OUTPUT
157 158
E S I0 I1 Y Y
HXXXLH LLLXLH LLHXHL LHXLLH LHXHHL
NOTE: H = High Voltage Level, L = Low Voltage Level, X = Don’t Care
2
3
5 6
10
13
14
11
4
7
12
9
4Y
3Y
2Y
1Y
1Y
4Y
3Y
2Y
HC/HCT
157
HC/HCT
158
1I
0
1I
1
2I
0
2I
1
3I
0
3I
1
4I
0
4I
1
S E
115
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V
DC Input Diode Current, I
IK
For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Diode Current, I
OK
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA
DC Output Source or Sink Current per Output Pin, I
O
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, I
CC orIGND
. . . . . . . . . . . . . . . . . .±50mA
Operating Conditions
Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, V
CC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V
CC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
DC Electrical Specifications
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40oC TO 85oC -55oCTO125oC
UNITSV
I
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HC TYPES
High Level Input Voltage
V
IH
- - 2 1.5 - - 1.5 - 1.5 - V
4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V
Low Level Input Voltage
V
IL
- - 2 - - 0.5 - 0.5 - 0.5 V
4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V
High Level Output Voltage CMOS Loads
V
OH
VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output Voltage TTL Loads
- - ---- - - - V
-4 4.5 3.98 - - 3.84 - 3.7 - V
-5.2 6 5.48 - - 5.34 - 5.2 - V
Low Level Output Voltage CMOS Loads
V
OL
VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output Voltage TTL Loads
- - ---- - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V
5.2 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage Current
I
I
VCC or
GND
-6--±0.1 - ±1-±1µA
Quiescent Device Current
I
CC
VCC or
GND
0 6 - - 8 - 80 - 160 µA
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
5
HCT TYPES
High Level Input Voltage
V
IH
- - 4.5 to
5.5
2--2- 2 - V
Low Level Input Voltage
V
IL
- - 4.5 to
5.5
- - 0.8 - 0.8 - 0.8 V
High Level Output Voltage CMOS Loads
V
OH
VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V
High Level Output Voltage TTL Loads
-4 4.5 3.98 - - 3.84 - 3.7 - V
Low Level Output Voltage CMOS Loads
V
OL
VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Low Level Output Voltage TTL Loads
4 4.5 - - 0.26 - 0.33 - 0.4 V
Input Leakage Current
I
I
VCCand
GND
0 5.5 - ±0.1 - ±1-±1µA
Quiescent Device Current
I
CC
VCC or
GND
0 5.5 - - 8 - 80 - 160 µA
Additional Quiescent Device Current Per Input Pin: 1 Unit Load
I
CC
V
CC
-2.1
- 4.5 to
5.5
- 100 360 - 450 - 490 µA
NOTE: For dual-supply systems theoretical worst case (V
I
= 2.4V, VCC = 5.5V) specification is 1.8mA.
DC Electrical Specifications (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C -40oC TO 85oC -55oCTO125oC
UNITSV
I
(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX
HCT Input Loading Table
INPUT
UNIT LOADS
HCT157 HCT158
I (All) 0.95 0.4
E 0.6 0.6 S 3 2.8
NOTE: Unit Load is I
CC
limit specified in DC Electrical Table,e.g.,
360µA max at 25oC.
Switching Specifications Input t
r
, tf = 6ns
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
HC/HCT157 TYPES
Propagation Delay (Figure 1) t
PLH,tPHLCL
= 50pF 2 - - 125 - 155 - 190 ns
Data to Output 4.5 - - 25 - 31 - 38 ns
HC157 CL=15pF 5 - 10 - - - - - ns
HCT157 - 12 - - - - - ns
CL= 50pF 6 - - 21 - 26 - 32 ns
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
6
Enable to Output t
PLH,tPHLCL
= 50pF 2 - - 135 - 170 - 205 ns
4.5 - - 27 - 34 - 41 ns
HC157 CL=15pF 5 - 11 - - - - - ns
HCT157 - 12 - - - - - ns
CL= 50pF 6 - - 23 - 29 - 35 ns
Select to Output t
PLH,tPHLCL
= 50pF 2 - - 145 - 180 - 220 ns
4.5 - - 29 - 36 - 44 ns
HC157 CL=15pF 5 - 12 - - - - - ns
HCT157 - 15 - - - - - ns
CL= 50pF 6 - - 25 - 31 - 38 ns
Power Dissipation Capacitance (Notes 4, 5)
C
PD
-5
HC157 - 62 - - - - - pF
HCT157 - 70 - - - - - pF
HC/HCT158 TYPES
Data to Output t
PLH,tPHLCL
= 50pF 2 - - 140 - 175 - 210 ns
4.5 - - 28 - 35 - 42
HC158 CL=15pF 5 - 11 - - - - - ns
HCT 158 - 13 - - - - - ns
CL= 50pF 6 - - 24 - 30 - 36 ns
Enable to Output t
PLH,tPHLCL
= 50pF 2 - - 160 - 200 - 240 ns
4.5 - - 32 - 40 - 48 ns
HC158 CL=15pF 5 - 13 - - - - - ns
HCT 158 - 15 - - - - - ns
CL= 50pF 6 - - 27 - 34 - 41 ns
Select to Output t
PLH,tPHLCL
= 50pF 2 - - 150 - 190 - 225 ns
4.5 - - 30 - 38 - 45 ns
HC158 CL=15pF 5 - 12 - - - - - ns
HCT 158 - 14 - - - - - ns
CL= 50pF 6 - - 26 - 33 - 38 ns
Output Transition Time t
TLH,tTHLCL
= 50pF 2 - - 75 - 95 - 110 ns
4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns
Power Dissipation Capacitance (Notes 4, 5)
C
PD
-5
HC158 - 35 - - - - - pF
HCT 158 - 35 - - - - - pF
Input Capacitance C
IN
CL= 50pF - - - 10 - 10 - 10 pF
NOTES:
4. CPD is used to determine the dynamic power consumption, per multiplexer.
5. PD = V
CC
2
fi(CPD + CL) where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
Switching Specifications Input t
r
, tf = 6ns (Continued)
PARAMETER SYMBOL
TEST
CONDITIONS
V
CC
(V)
25oC -40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN MAX MIN MAX
CD74HC157, CD74HCT157, CD74HC158, CD74HCT158
7
Test Circuits and Waveforms
FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-
TION DELAY TIMES, COMBINATION LOGIC
FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
PHL
t
PLH
t
THL
t
TLH
90% 50% 10%
50%
10%
INVERTING
OUTPUT
INPUT
GND
V
CC
tr = 6ns tf = 6ns
90%
t
PHL
t
PLH
t
THL
t
TLH
2.7V
1.3V
0.3V
1.3V
10%
INVERTING
OUTPUT
INPUT
GND
3V
tr = 6ns
t
f
= 6ns
90%
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1998, Texas Instruments Incorporated
Loading...