Texas Instruments CD74HCT147E, CD74HC147M96, CD74HC147M, CD74HC147E, CD54HC147F3A Datasheet

CD74HC147,

[ /Title
(CD74
HC147
,
CD74
HCT14

7)
/Sub­ject
(High
Speed
CMOS
Logic
10-to-4
Line
Prior­ity
Encode
r)
/Autho
r ()
/Key­words
(High
Speed
CMOS
Logic
10-to-4
Line
Prior­ity
Encode
r, High
Speed
CMOS
Logic
10-to-4
Line
Prior­ity

Data sheet acquired from Harris Semiconductor
SCHS149

September 1997

Features

• Buffered Inputs and Outputs

• Typical Propagation Delay: 13ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

= 30%, NIH = 30% of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

Pinout

Description

The Harris CD74HC147and CD74HCT147 are high speed
silicon-gate CMOS devices and are pin-compatible with low
power Schottky TTL (LSTTL).

The CD74HC147 and CD74HCT147 9-input priority
encoders accept data from nine active LOW inputs (l
and provide binary representation on the four active LOW
inputs (

C to 125oC

OH

CD74HC147, CD74HCT147

1

I4

2

I5

3

I6

4

I7

5

I8

6

Y2

7

Y1

8

GND

when two or more inputs are simultaneously active, the input
with the highest priority is represented on the output, with
input line l

These devices provide the 10-line to 4-line priority encoding
function by use of the implied decimal “zero”. The “zero” is
encoded when all nine data inputs are HIGH, forcing all four
outputs HIGH.

Ordering Information

CC

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC147E -55 to 125 16 Ld PDIP E16.3
CD74HCT147E -55 to 125 16 Ld PDIP E16.3
CD74HC147M -55 to 125 16 Ld SOIC M16.15
CD74HCT147M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire partnumber. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waferor die forthis part numberis available whichmeets all elec­trical specifications. Please contact your local sales office or
Harris customer service for ordering information.

(PDIP, SOIC)

TOP VIEW

16
15
14
13
12
11
10

9

CD74HCT147

High Speed CMOS Logic

10-to-4 Line Priority Encoder

to l9)

1

Y0 to Y3). A priority is assigned to each input so that

having the highest priority.

9

PKG.

NO.

V

CC

NC
Y3
I3
I2
I1
I9
Y0

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1997

1

File Number 1773.1

Functional Diagram

I1 I2 I3 I4 I5 I6 I7 I8 I9 Y3 Y2 Y1 Y0

HHHHHHHHHHHHH

CD74HC147, CD74HCT147

11

I1

12

I2

13

I3

1

I4

2

I5

3

I6

4

I7

5

I8

10

I9

TRUTH TABLE

INPUTS OUTPUTS

9

7

6

14

GND = 8

= 16

V

CC

Y0

Y1

Y2

Y3

XXXXXXXXLLHHL
XXXXXXXLHLHHH
XXXXXXLHHHLLL
XXXXXLHHHHLLH
XXXXLHHHHHLHL
XXXLHHHHHHLHH
XXLHHHHHHHHLL
XLHHHHHHHHHLH

LHHHHHHHHHHHL

NOTE: H = High Logic Level, L = Low Logic Level, X = Don’t Care

2

CD74HC147, CD74HCT147

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

25

C -40oC TO 85oC -55oC TO 125oC

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1 µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC147, CD74HCT147

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input

V

IH

V

IL

Voltage
High Level Output

Voltage

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output

V

OL

Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent

I

I

I

CC

∆I

CC

Device Current Per
Input Pin: 1 Unit Load

NOTE: For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

4 4.5 - - 0.26 - 0.33 - 0.4 V

VCCand

0 5.5 - ±0.1 - ±1-±1 µA

GND

VCC or

0 5.5 - - 8 - 80 - 160 µA

GND

V

CC

- 4.5 to

-2.1

o

C -40oC TO 85oC -55oC TO 125oC

V

CC

25

(V)

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

UNITSV

HCT Input Loading Table

INPUT UNIT LOADS

I1, I2, I3, I6, I

I4, I5, I8, I

7

9

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Switching Specifications Input t

r

PARAMETER SYMBOL

HC TYPES

Propagation Delay,

t

PLH,tPHL

Input to Output (Figure 1)

Transition Times

t

TLH

, t

THL

(Figure 1)

Input Capacitance C

IN

1.1

1.5

, tf = 6ns

TEST

CONDITIONS VCC(V)

CL= 50pF 2 - - 160 - 200 - 240 ns

4.5 - - 32 - 40 - 48 ns
5 - 13 - - - - - ns
6 - - 27 - 34 - 41 ns

CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

- - - - 10 - 10 - 10 pF

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC147, CD74HCT147

Switching Specifications Input t

, tf = 6ns (Continued)

r

TEST

PARAMETER SYMBOL

Power Dissipation Capaci-

C

CONDITIONS VCC(V)

PD

-5-32-----pF
tance
(Notes 4, 5)

HCT TYPES

Propagation Delay,
Input to Output (Figure 2)

Transition Times (Figure 2) t
Input Capacitance C
Power Dissipation Capaci-

t

PLH

TLH

, t

CL= 50pF 4.5 - - 35 - 44 - 53 ns

PHL

5 - 14 - - - - - ns

, t

IN

C

PD

CL= 50pF 4.5 - - 15 - 19 - 22 ns

THL

- - - - 10 - 10 - 10 pF

-5-42-----pF
tance
(Notes 4, 5)

NOTES:

4. CPD is used to determine the dynamic power consumption, per gate.

5. PD = V

2

fi(CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

25oC -40oC TO 85oC -55oC TO 125oC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

2.7V

1.3V

0.3V

PHL

UNITSMIN TYP MAX MIN MAX MIN MAX

FIGURE 6. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

FIGURE 7. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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