Texas Instruments CD74HCT139M96, CD74HCT139M, CD74HCT139E, CD74HC139M96, CD74HC139M Datasheet

CD74HC139,

/
j

[ /Title
(CD74
HC139
,
CD74
HCT13

9)
Sub­ect

(High
Speed
CMOS
Logic
Dual
2-to-4
Line
Decod

Data sheet acquired from Harris Semiconductor
SCHS148A

September 1997 - Revised May 1999

Features

• Multifunction Capability

- Binary to 1 of 4 Decoders or 1 to 4 Line
Demultiplexer

• Active Low Mutually Exclusive Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High NoiseImmunity: N

V

= 5V

CC

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

• Memory Decoding, Data Routing, Code Conversion

= 30%, NIH= 30%of VCCat

IL

≤ 1µA at VOL, V

l

o

C to 125oC

OH

CD74HCT139

High-Speed CMOS Logic

Dual 2-to-4 Line Decoder/Demultiplexer

Description

The CD74HC139 and CD74HCT139 devices contain two
independent binary to one of four decoders each with a
single active low enable input (
inputs (1A0 and 1A1 or 2A0 and 2A1) cause one of the four
normally high outputs to go low.

If the enable input is high all four outputs remain high. For
demultiplexer operation the enable input is the data input.
The enable input also functions as a chip select when these
devices are cascaded. This device is functionally the same
as the CD4556B and is pin compatible with it.

The outputs of these devices can drive 10 low power
Schottky TTL equivalent loads. The 74HCT logic family is
functionally as well as pin equivalent to the 74LS logic family.

Ordering Information

PART NUMBER TEMP. RANGE (oC) PACKAGE

CD74HC139E -55 to 125 16 Ld PDIP E16.3
CD74HCT139E -55 to 125 16 Ld PDIP E16.3
CD74HC139M -55 to 125 16 Ld SOIC M16.15
CD74HCT139M -55 to 125 16 Ld SOIC M16.15

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Die is available which meets all electrical specifications. Please
contact your local sales office or customer service for ordering
information.

1E or 2E). Data on the select

PKG.

NO.

Pinout

CD74HC139, CD74HCT139

(PDIP, SOIC)

TOP VIEW

16

1

1E

1A0

2

1A1

3
4

1Y0

5

1Y1

6

1Y2

7

1Y3

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Texas Instruments Incorporated 1999

1

V

CC

15

2E

14

2A0

13

2A1

12

2Y0

11

2Y1

10

2Y2

9

2Y3

Functional Diagram

CD74HC139, CD74HCT139

4 (12)

2 (14)

A0

3 (13)

A1

1 (15)

E

TRUTH TABLE

INPUTS ENABLE SELECT OUTPUTS

EA1A0Y3 Y2 Y1 Y0

0001110
0011101
0101011

5 (11)
6 (10)
7 (9)

Y0

Y1
Y2
Y3

Logic Diagram

0110111
1XX1111

NOTE: X = Don’t Care, Logic 1 = High, Logic 0 = Low

2 (14)

A0

3 (13)

A1

1 (15)

E

4 (12)
Y0

5 (11)
Y1

6 (10)
Y2

7 (9)
Y3

2

CD74HC139, CD74HCT139

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, I

CC orIGND

. . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

3. θJA is measured with the component mounted on an evaluation PC board in free air.

CC

Thermal Resistance (Typical, Note 3) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

TEST

CONDITIONS

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

V

CC

(V)

o

C -40oC TO 85oC -55oCTO125oC

25

UNITSV

- - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

-6--±0.1 - ±1-±1µA

GND

VCC or

0 6 - - 8 - 80 - 160 µA

GND

3

CD74HC139, CD74HCT139

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage

V

IH

V

IL

V

OH

CMOS Loads
High Level Output

Voltage
TTL Loads

Low Level Output
Voltage

V

OL

CMOS Loads
Low Level Output

Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per

I

I

I

CC

∆I

CC

Input Pin: 1 Unit Load
(Note 4)

NOTE:

4. For dual-supply systems theoretical worst case (V

(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

I

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

o

C -40oC TO 85oC -55oCTO125oC

V

CC

(V)

25

UNITSV

2--2- 2 - V

5.5

- - 0.8 - 0.8 - 0.8 V

5.5

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - ±0.1 - ±1-±1µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

- 100 360 - 450 - 490 µA

5.5

= 2.4V, VCC = 5.5V) specification is 1.8mA.

I

HCT Input Loading Table

INPUT UNIT LOADS

All 0.7

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table,e.g.,
360µA max at 25oC.

Switching Specifications Input t

PARAMETER SYMBOL

HC TYPES

Propagation Delay t

A0, A1 to Outputs 4.5 - - 29 - 36 - 44 ns

E to Outputs t

Select to Output t
Enable to Output t

, tf = 6ns

r

CONDITIONS

PLH,tPHLCL

PLH,tPHLCL

PLH,tPHLCL
PLH,tPHLCL

TEST

o

C

V

CC

25

-40oC TO
85oC

-55oC TO
125oC

(V)

= 50pF 2 - - 145 - 180 - 220 ns

6 - - 25 - 31 - 38 ns

= 50pF 2 - - 135 - 170 - 205 ns

4.5 - - 27 - 34 - 41 ns
6 - - 23 - 29 - 35 ns

= 15pF 5 - 12 - - - - - ns
= 15pF 5 - 11 - - - - - ns

UNITSMIN TYP MAX MIN MAX MIN MAX

4

CD74HC139, CD74HCT139

Switching Specifications Input t

PARAMETER SYMBOL

Output Transition Time (Figure 1) t

Power Dissipation
Capacitance, (Notes 5, 6)

Input Capacitance C

HCT TYPES

Propagation Delay

A0, A1 to Outputs t

E to Outputs t

Select to Output t
Enable to Output t

Output Transition Time
(Figure 2)

Power Dissipation
Capacitance, (Notes 5, 6)

Input Capacitance C

NOTES:

5. C

is used to determine the dynamic power consumption, per decoder/demux.

PD

6. PD = V

2

fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

CC

TLH

PLH,tPHLCL
PLH,tPHLCL

t

TLH

, tf = 6ns (Continued)

r

TEST

CONDITIONS

, t

THLCL

C

PD

IN

,

PLH

t

PHL

,

PLH

t

PHL

= 50pF 2 - - 75 - 95 - 110 ns

- 5 -55- - - - - pF

- - - - 10 - 10 - 10 pF

CL= 50pF 4.5 - - 34 - 43 - 51 ns

CL= 50pF 4.5 - - 34 - 43 - 51 ns

= 15pF 5 - 14 - - - - - ns
= 15pF 5 - 14 - - - - - ns

, t

THLCL

C

PD

IN

= 50pF 4.5 - - 15 - 19 - 22 ns

- 5 -59- - - - - pF

- - - - 10 - 10 - 10 pF

o

C

V

CC

25

-40oC TO
85oC

(V)

-55oC TO
125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

4.5 - - 15 - 19 - 22 ns
6 - - 13 - 16 - 19 ns

Test Circuits and Waveforms

tr = 6ns tf = 6ns

V

t

CC

GND

TLH

t

PHL

90%
50%
10%

t

90%

50%

10%

PLH

INPUT

t

INVERTING

OUTPUT

THL

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

= 6ns

t

PLH

t

f

1.3V

10%

90%

t

3V

GND

TLH

tr = 6ns

INPUT

t

INVERTING

OUTPUT

THL

t

PHL

2.7V

1.3V

0.3V

FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

5

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Copyright  1999, Texas Instruments Incorporated