TEXAS INSTRUMENTS CD74HC137 Technical data

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CD74HC137, CD74HCT137,

CD54HC237, CD74HC237,

[ /Title (CD74 HC137 ,

D74

C HCT13 7, CD74 HC237 ,

D74

C HCT23

7) /Subject (High Speed

Data sheet acquired from Harris Semiconductor SCHS146F

March 1998 - Revised October 2003

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for ’HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V 15pF, T

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

- CMOS Input Compatibility, I

= 25oC (CD74HC237)

at VCC = 5V

= 0.8V (Max), VIH = 2V (Min)

= 30%, NIH = 30%, of V

≤ 1µA at VOL, V

= 5V,

CD74HCT237

High-Speed CMOS Logic, 3- to 8-Line

Decoder/Demultiplexer with Address Latches

Both circuits have three binary selectinputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes. A “Low” LE makes the output transparent to the input and the circuit functions as a one-of-eight decoder. Two Output

C to 125oC

Enable inputs ( cascading and to facilitate demultiplexing. The demultiplexing function is accomplished by using the A A

inputs to select the desired output and using one of the

other Output Enable inputs as the data input while holding the other Output Enable input in its active state. In the CD74HC137 and CD74HCT137 the selected output is a “Low”; in the ’HC237 and CD74HCT237 the selected output is a “High”.

Ordering Information

PART NUMBER

CD54HC237F3A -55 to 125 16 Ld CERDIP CD74HC137E -55 to 125 16 Ld PDIP CD74HC137PW -55 to 125 16 Ld TSSOP CD74HC137PWR -55 to 125 16 Ld TSSOP CD74HC137PWT -55 to 125 16 Ld TSSOP CD74HC237E -55 to 125 16 Ld PDIP CD74HC237M -55 to 125 16 Ld SOIC CD74HC237MT -55 to 125 16 Ld SOIC

OE1and OE0) are provided to simplify

0,A1

TEMP. RANGE

(oC) PACKAGE

Description

The CD74HC137, CD74HCT137, ’HC237, and CD74HCT237 are high speed silicon gate CMOS decoders well suited to memory address decoding or data routing applications. Both circuits feature low power consumption usually associated with CMOS circuitry, yet have speeds comparable to low power Schottky TTL logic.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures. Copyright

CD74HC237M96 -55 to 125 16 Ld SOIC CD74HC237NSR -55 to 125 16 Ld SOP CD74HC237PW -55 to 125 16 Ld TSSOP CD74HC237PWR -55 to 125 16 Ld TSSOP CD74HC237PWT -55 to 125 16 Ld TSSOP CD74HCT137E -55 to 125 16 Ld PDIP CD74HCT137MT -55 to 125 16 Ld SOIC CD74HCT137M96 -55 to 125 16 Ld SOIC CD74HCT237E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96 and R denote tape and reel. The sufﬁx T denotes a small-quantity reel of 250.

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Pinout

CD54HC237 (CERDIP)

CD74HC137 (PDIP, TSSOP)

CD74HCT137 (PDIP, SOIC)

CD74HC237 (PDIP, SOIC, SOP, TSSOP)

CD74HCT237 (PDIP)

TOP VIEW

A A A

LE OE OE

GND

4 5

Functional Diagram

3-BIT

LATCH

GND = 8

= 16

DECODER

1 OF 8

HC/HCT HC/HCT

237 137

’HC137, ’HCT137 TRUTH TABLE

INPUTS OUTPUTS

LE OE

XXHXXXHHHHHHHH XLXXXXHHHHHHHH LHLLLLLHHHHHHH LHLLLHHLHHHHHH LHLLHLHHLHHHHH LHLLHHHHHLHHHH LHLHLLHHHHLHHH LHLHLHHHHHHLHH LHLHHLHHHHHHLH LHLHHHHHHHHHHL H H L X X X Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

’HC237, ’HCT237 TRUTH TABLE

INPUTS OUTPUTS

LE OE

XXHXXXLLLLLLLL XLXXXXLLLLLLLL LHLLLLHLLLLLLL LHLLLHLHLLLLLL LHLLHLLLHLLLLL LHLLHHLLLHLLLL LHLHLLLLLLHLLL LHLHLHLLLLLHLL LHLHHLLLLLLLHL LHLHHHLLLLLLLH H H L X X X Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Functional Block Diagram

p n

A1 LATCH

A2 LATCH

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

DC Electrical Speciﬁcations

PARAMETER SYMBOL

HC TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

TEST

CONDITIONS

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

GND

(V)

4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V

-6--±0.1 - ±1-±1 µA

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

DC Electrical Speciﬁcations (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device Current

HCT TYPES

High Level Input Voltage

Low Level Input Voltage

High Level Output Voltage CMOS Loads

High Level Output Voltage TTL Loads

Low Level Output Voltage CMOS Loads

Low Level Output Voltage TTL Loads

Input Leakage Current

Quiescent Device Current

Additional Quiescent Device Current Per Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

∆I

(Note 2)

VCC or

GND

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

-2.1

0 6 - - 8 - 80 - 160 µA

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

(V)

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2--2- 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 1.5

NOTE: Unit Load is ∆ICClimit speciﬁed in DC Electrical Table, e.g., 360µA max at 25oC.

Prerequisite For Switching Speciﬁcations

PARAMETER SYMBOL

HC TYPES

Anto LE Setup Time t

An to LE Hold Time t

(V)

250- -65-75- ns

4.5 10 - - 13 - 15 - ns 6 9 - - 11 - 13 - ns 230- -40-45- ns

4.56--8-9-ns 65--7-8-ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Prerequisite For Switching Speciﬁcations (Continued)

PARAMETER SYMBOL

LE Pulse Width t

(V)

250- -65-75- ns

4.5 10 - - 13 - 15 - ns 6 9 - - 1 - 13 - ns

HCT TYPES

An to LE Setup Time t

4.5 10 - - 13 - 15 - ns

An to LE Hold Time

CD74HCT137 4.5 7 - - 9 - 11 - ns CD74HCT237 t

LE Pulse Width t

4.55--5-5-ns

4.5 10 - - 13 - 15 - ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Switching Speciﬁcations Input t

, tf = 6ns

-40oC TO

PARAMETER SYMBOL

TEST

CONDITIONS VCC(V)

25oC

85oC -55oC TO 125oC

HC TYPES

Propagation Delay

PLH,tPHLCL

= 50pF 2 - - 180 - 225 - 270 ns

CD74HC137, CD74HCT137

An to any Y 4.5 - - 36 - 45 - 54 ns

6 - - 31 - 38 - 46 ns

Propagation Delay

PLH,tPHLCL

= 50pF 2 - - 160 - 200 - 240 ns

’HC237, CD74HCT237

An to any Y 4.5 - - 32 - 40 - 48 ns

6 - - 27 - 34 - 41 ns Address to Output CD74HC137 t ’HC237 t

OE0 to any Y or Y t

, t

PLH

PHLCL

, t

PLH

PHLCL

PLH,tPHLCL

= 15pF 5 5 15 - - - - - ns = 15pF 5 - 13 - - - - - ns

= 50pF 2 - - 145 - 180 - 220 ns

4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns

OE1 to any Y or Y t

TLH

, t

THLCL

= 50pF 2 - - 145 - 180 - 220 ns

4.5 - - 29 - 36 - 44 ns 6 - - 25 - 31 - 38 ns

LE to any Y or Y t

TLH

, t

THLCL

= 50pF 2 - - 190 - 240 - 285 ns

4.5 - - 38 - 48 - 57 ns 6 - - 32 - 41 - 48 ns

Power Dissipation Capacitance, (Notes 3, 4)

CD74HC137 C ’HC237 C

Output Transition Time t

TLH

CL = 15pF 5 - 19 - - - - - pF

CL = 15pF 5 - 23 - - - - - pF

, t

THLCL

= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns 6 - - 13 - 16 - 19 ns

Input Capacitance C

- - - - 10 - 10 - 10 pF

UNITSMIN TYP MAX MIN MAX MIN MAX

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Switching Speciﬁcations Input t

, tf = 6ns (Continued)

TEST

PARAMETER SYMBOL

CONDITIONS VCC(V)

HCT TYPES

Propagation Delay An to any Y or Y Address to Output

OE0to any Y (HC137) t OE0to any Y (HC237) t OE1to any Y (HC137) t OE1to any Y (HC237) t LE to any Y (HC137) t LE to any Y (HC237) t

PLH

PLH PLH PLH TLH TLH TLH TLH

, t

PHLCL

, t

PHLCL

, t

PHLCL

, t

PHLCL

, t

THLCL

, t

THLCL

, t

THL

, t

THLCL

= 50pF 4.5 - - 38 - 48 - 57 ns = 15pF 5 - 16 - - - - - ns = 50pF 4.5 - - 35 - 44 - 53 ns = 50pF 4.5 - - 33 - 41 - 60 ns

= 50pF 4.5 - - 37 - 46 - 56 ns = 50pF 4.5 - - 35 - 44 - 53 ns

CL = 50pF 4.5 - - 44 - 55 - 66 ns

= 50pF 4.5 - - 42 - 53 - 63 ns

Power Dissipation Capacitance, (Notes 3, 4)

CD74HC137 C

’HC237 C

Output Transition Time t

TLH

Input Capacitance C

CL = 15pF 5 - 19 - - - - - pF

CL= 15pF 5 - 23 - - - - - pF

, t

THLCL

= 50pF 4.5 15 19 22 ns

- - - - 10 - 10 - 10 pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = V

fi(CPD + CL) where: fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

25oC

-40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

TLH

50%

GND

trC

CLOCK

10%

90%

50%

10%

tfC

tWL+ tWH=

50%

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 1. HC CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

tr = 6ns tf = 6ns

PHL

90% 50% 10%

90%

50%

10%

PLH

INPUT

THL

INVERTING

OUTPUT

FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC

+ tWH=

1.3V

GND

trCL= 6ns

CLOCK

0.3V

2.7V

1.3V

0.3V

= 6ns

fCL

1.3V

NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For f

, input duty cycle = 50%.

MAX

FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND

PULSE WIDTH

= 6ns

PLH

1.3V

10%

90%

GND

TLH

tr = 6ns

INPUT

INVERTING

OUTPUT

THL

2.7V

1.3V

0.3V

PHL

FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Test Circuits and Waveforms (Continued)

90%

PLH

TLH

tfC

50%

GND

H(L)

50%

SU(L)

90%

THL

GND

50%

10% t

PHL

GND

CLOCK

INPUT

DAT A

INPUT

SU(H)

OUTPUT

REM

SET, RESET OR PRESET

trC

90%

10%

H(H)

50%

50pF

FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

CLOCK

INPUT

DAT A

INPUT

SU(H)

OUTPUT

REM

SET, RESET

OR PRESET

trC

2.7V

0.3V

H(H)

1.3V

90%

PLH

1.3V

TLH

tfC

1.3V GND

H(L)

1.3V

SU(L)

90%

1.3V 10%

PHL

THL

GND

50pF

FIGURE 6. HCTSETUP TIMES, HOLD TIMES, REMOVAL TIME,

AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS

PACKAGE OPTION ADDENDUM

www.ti.com

28-Feb-2005

PACKAGING INFORMATION

Orderable Device Status

(1)

Package

Type

Package Drawing

Pins Package

Qty

Eco Plan

5962-8860601EA ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD54HC237F ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD54HC237F3A ACTIVE CDIP J 16 1 None Call TI Level-NC-NC-NC

CD74HC137E ACTIVE PDIP N 16 25 Pb-Free

CD74HC137PW ACTIVE TSSOP PW 16 90 Pb-Free

CD74HC137PWR ACTIVE TSSOP PW 16 2000 Pb-Free

CD74HC137PWT ACTIVE TSSOP PW 16 250 Pb-Free

CD74HC237E ACTIVE PDIP N 16 25 Pb-Free

CD74HC237M ACTIVE SOIC D 16 40 Pb-Free

CD74HC237M96 ACTIVE SOIC D 16 2500 Pb-Free

CD74HC237MT ACTIVE SOIC D 16 250 Pb-Free

CD74HC237NSR ACTIVE SO NS 16 2000 Pb-Free

CD74HC237PW ACTIVE TSSOP PW 16 90 Pb-Free

CD74HC237PWR ACTIVE TSSOP PW 16 2000 Pb-Free

CD74HC237PWT ACTIVE TSSOP PW 16 250 Pb-Free

CD74HCT137E ACTIVE PDIP N 16 25 Pb-Free

CD74HCT137M96 ACTIVE SOIC D 16 2500 Pb-Free

CD74HCT137MT ACTIVE SOIC D 16 250 Pb-Free

CD74HCT237E ACTIVE PDIP N 16 25 Pb-Free

(1)

The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in

a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.

(RoHS)

(2)

Lead/Ball Finish MSL Peak Temp

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-1-250C-UNLIM

CU NIPDAU Level-NC-NC-NC

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-2-260C-1 YEAR/

Level-1-235C-UNLIM

CU NIPDAU Level-NC-NC-NC

(3)

(2)

Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional

product content details.

None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements

for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight.

Addendum-Page 1

PACKAGE OPTION ADDENDUM

www.ti.com

(3)

MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder

temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

28-Feb-2005

Addendum-Page 2

MECHANICAL DATA

MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999

PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE

14 PINS SHOWN

0,65

1,20 MAX

0,30 0,19

4,50 4,30

PINS **

Seating Plane

0,15

0,05

DIM

0,10

6,60 6,20

0,10

0,15 NOM

0°–8°

2016

Gage Plane

0,25

0,75 0,50

A MAX

A MIN

NOTES: A. All linear dimensions are in millimeters.

B. This drawing is subject to change without notice. C. Body dimensions do not include mold flash or protrusion not to exceed 0,15. D. Falls within JEDEC MO-153

3,10

2,90

5,10

4,90

5,10

4,90

6,60

6,40

7,90

7,70

9,80

9,60

4040064/F 01/97

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security

Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless

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TEXAS INSTRUMENTS CD74HC137 Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual