TEXAS INSTRUMENTS CD74HC137 Technical data

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CD74HC137, CD74HCT137,

CD54HC237, CD74HC237,

[ /Title
(CD74
HC137
,

D74

C
HCT13
7,
CD74
HC237
,

D74

C
HCT23

7)
/Sub­ject
(High
Speed

Data sheet acquired from Harris Semiconductor
SCHS146F

March 1998 - Revised October 2003

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for ’HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V
15pF, T

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

- CMOS Input Compatibility, I

= 25oC (CD74HC237)

A

at VCC = 5V

V

= 0.8V (Max), VIH = 2V (Min)

IL

= 30%, NIH = 30%, of V

IL

≤ 1µA at VOL, V

l

CC

= 5V,

o

CD74HCT237

High-Speed CMOS Logic, 3- to 8-Line

Decoder/Demultiplexer with Address Latches

Both circuits have three binary selectinputs (A0, A1 and A2)
that can be latched by an active High Latch Enable (LE)
signal to isolate the outputs from select-input changes. A
“Low” LE makes the output transparent to the input and the
circuit functions as a one-of-eight decoder. Two Output

C to 125oC

CC

OH

Enable inputs (
cascading and to facilitate demultiplexing. The
demultiplexing function is accomplished by using the A
A

inputs to select the desired output and using one of the

2

other Output Enable inputs as the data input while holding
the other Output Enable input in its active state. In the
CD74HC137 and CD74HCT137 the selected output is a
“Low”; in the ’HC237 and CD74HCT237 the selected output is
a “High”.

Ordering Information

PART NUMBER

CD54HC237F3A -55 to 125 16 Ld CERDIP
CD74HC137E -55 to 125 16 Ld PDIP
CD74HC137PW -55 to 125 16 Ld TSSOP
CD74HC137PWR -55 to 125 16 Ld TSSOP
CD74HC137PWT -55 to 125 16 Ld TSSOP
CD74HC237E -55 to 125 16 Ld PDIP
CD74HC237M -55 to 125 16 Ld SOIC
CD74HC237MT -55 to 125 16 Ld SOIC

OE1and OE0) are provided to simplify

0,A1

TEMP. RANGE

(oC) PACKAGE

,

Description

The CD74HC137, CD74HCT137, ’HC237, and
CD74HCT237 are high speed silicon gate CMOS decoders
well suited to memory address decoding or data routing
applications. Both circuits feature low power consumption
usually associated with CMOS circuitry, yet have speeds
comparable to low power Schottky TTL logic.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© 2003, Texas Instruments Incorporated

CD74HC237M96 -55 to 125 16 Ld SOIC
CD74HC237NSR -55 to 125 16 Ld SOP
CD74HC237PW -55 to 125 16 Ld TSSOP
CD74HC237PWR -55 to 125 16 Ld TSSOP
CD74HC237PWT -55 to 125 16 Ld TSSOP
CD74HCT137E -55 to 125 16 Ld PDIP
CD74HCT137MT -55 to 125 16 Ld SOIC
CD74HCT137M96 -55 to 125 16 Ld SOIC
CD74HCT237E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The suffixes 96
and R denote tape and reel. The suffix T denotes a small-quantity
reel of 250.

1

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Pinout

CD54HC237 (CERDIP)

CD74HC137 (PDIP, TSSOP)

CD74HCT137 (PDIP, SOIC)

CD74HC237 (PDIP, SOIC, SOP, TSSOP)

CD74HCT237 (PDIP)

TOP VIEW

16

A
A
A

LE
OE
OE

GND

1

0

2

1

3

3

4
5

1

6

0

7

Y

7

8

V

CC

15

Y

0

14

Y

1

13

Y

2

12

Y

3

11

Y

4

10

Y

5

9

Y

6

Functional Diagram

1

A

0

2

3-BIT

A

1

LATCH

OE

OE

A

LE

3

2

1

0

4

5

6

GND = 8

V

= 16

CC

DECODER

1 OF 8

HC/HCT HC/HCT

237 137

15

Y

Y

0

0

14

Y

Y

1

1

13

Y

Y

2

2

12

Y

Y

3

3

11

Y

Y

4

4

10

Y

Y

5

5

9

Y

Y

6

6

7

Y

Y

7

7

’HC137, ’HCT137 TRUTH TABLE

INPUTS OUTPUTS

LE OE

OE

0

A

1

A

2

A

1

0

Y

0

Y

Y

1

Y

2

Y

3

Y

4

5

Y

Y

6

XXHXXXHHHHHHHH
XLXXXXHHHHHHHH
LHLLLLLHHHHHHH
LHLLLHHLHHHHHH
LHLLHLHHLHHHHH
LHLLHHHHHLHHHH
LHLHLLHHHHLHHH
LHLHLHHHHHHLHH
LHLHHLHHHHHHLH
LHLHHHHHHHHHHL
H H L X X X Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

7

’HC237, ’HCT237 TRUTH TABLE

INPUTS OUTPUTS

LE OE

OE

0

A

1

A

2

A

1

0

Y

0

Y

Y

1

Y

2

Y

3

Y

4

5

Y

Y

6

7

XXHXXXLLLLLLLL
XLXXXXLLLLLLLL
LHLLLLHLLLLLLL
LHLLLHLHLLLLLL
LHLLHLLLHLLLLL
LHLLHHLLLHLLLL
LHLHLLLLLLHLLL
LHLHLHLLLLLHLL
LHLHHLLLLLLLHL
LHLHHHLLLLLLLH
H H L X X X Depends upon the address previously applied while LE was at a logic low.

H = High Voltage Level, L = Low Voltage Level, X = Don’t Care

2

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Functional Block Diagram

LE

1

A

0

p
n

LE

LE

A

0

A

0

p
n

15

Y

0

14

Y

1

13

Y

2

OE

OE

A

A

LE

LE

A

2

1

A1 LATCH

1

A

0

12

Y

3

11

Y

4

10

A

3

2

A2 LATCH

2

A

2

Y

5

9

Y

6

LE

4

LE

7

Y

7

5

1

6

0

3

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

IK

OK

O

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, V

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

CC

Package Thermal Impedance, θJA(see Note 1):

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .64oC/W

PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . 108oC/W

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC

(SOIC - Lead Tips Only)

CC

DC Electrical Specifications

PARAMETER SYMBOL

HC TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

V

IH

V

IL

V

OH

V

OL

I

I

TEST

CONDITIONS

- - 2 1.5 - - 1.5 - 1.5 - V

- - 2 - - 0.5 - 0.5 - 0.5 V

VIHor VIL-0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

- - ---- - - - V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

VIHor VIL0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

- - ---- - - - V
4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

VCC or

GND

V

CC

(V)

4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V

4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V

-6--±0.1 - ±1-±1 µA

25oC -40oC TO 85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

4

CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237

DC Electrical Specifications (Continued)

TEST

CONDITIONS

PARAMETER SYMBOL

Quiescent Device
Current

HCT TYPES

High Level Input
Voltage

Low Level Input
Voltage

High Level Output
Voltage
CMOS Loads

High Level Output
Voltage
TTL Loads

Low Level Output
Voltage
CMOS Loads

Low Level Output
Voltage
TTL Loads

Input Leakage
Current

Quiescent Device
Current

Additional Quiescent
Device Current Per
Input Pin: 1 Unit Load

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

I

CC

V

IH

V

IL

V

OH

V

OL

I

I

I

CC

∆I

CC

(Note 2)

VCC or

GND

- - 4.5 to

- - 4.5 to

VIHor VIL-0.02 4.5 4.4 - - 4.4 - 4.4 - V

VIHor VIL0.02 4.5 - - 0.1 - 0.1 - 0.1 V

VCCand

GND

VCC or

GND

V

CC

-2.1

0 6 - - 8 - 80 - 160 µA

-4 4.5 3.98 - - 3.84 - 3.7 - V

4 4.5 - - 0.26 - 0.33 - 0.4 V

0 5.5 - - ±0.1 - ±1-±1 µA

0 5.5 - - 8 - 80 - 160 µA

- 4.5 to

V

CC

(V)

5.5

5.5

5.5

25oC -40oC TO 85oC -55oC TO 125oC

2--2- 2 - V

- - 0.8 - 0.8 - 0.8 V

- 100 360 - 450 - 490 µA

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 1.5

NOTE: Unit Load is ∆ICClimit specified in DC Electrical Table, e.g.,
360µA max at 25oC.

Prerequisite For Switching Specifications

V

PARAMETER SYMBOL

HC TYPES

Anto LE Setup Time t

An to LE Hold Time t

SU

H

CC

(V)

250- -65-75- ns

4.5 10 - - 13 - 15 - ns
6 9 - - 11 - 13 - ns
230- -40-45- ns

4.56--8-9-ns
65--7-8-ns

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

5