Texas Instruments CD74HCT02M96, CD74HCT02M, CD74HCT02E, CD74HC02M96, CD74HC02M Datasheet

CD74HC02,

/

[ /Title
(CD74H
C02,
CD74H
CT02)

Subject
(High
Speed
CMOS
Logic
Quad
Two-

Data sheet acquired from Harris Semiconductor
SCHS125

March 1998

Features

• Buffered Inputs

• Typical Propagation Delay: 7ns at V
C

= 15pF, TA = 25oC

L

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

• Balanced Propagation Delay and Transition Times

• Significant Power Reduction Compared to LSTTL
Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, NIH = 30% of V

IL

CC

= 5V,

o

C to 125oC

CC

CD74HCT02

High Speed CMOS Logic

Quad Two-Input NOR Gate

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,
V

= 0.8V (Max), VIH = 2V (Min)

IL

- CMOS Input Compatibility, I

• Related Literature

- CD54HC02F3A and CD54HCT02F3A Military
Data Sheet, Document Number 3754

Description

The Harris CD74HC02, CH74HCT02 logic gates utilize
silicon-gate CMOS technology to achieve operating speeds
similar to LSTTL gates with the low power consumption of
standard CMOSintegrated circuits.All deviceshave theability
to drive 10 LSTTL loads. The 74HCT logic family is

≤ 1µA at VOL, V

l

OH

Pinout

CD74HC02, CD74HCT02

(PDIP, SOIC)

TOP VIEW

1Y

1
2

1A
1B

3

2Y

4

2A

5

2B

6

GND

7

V

14

CC

4Y

13

4B

12

4A

11

3Y

10

3B

9

3A

8

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright

© Harris Corporation 1998

1

File Number 1647.1

Functional Diagram

CD74HC02, CD74HCT02

1Y

1A

1B

2Y

2A

2B

GND

1

2

3

4

5

6

7

14

V

CC

13

4Y

12

4B

11

4A

10

3Y

9

3B

8

3A

TRUTH TABLE

INPUTS OUTPUT

nA nB nY

LLH
LHL
HLL
HHL

Logic Diagram

NOTE: H = High Voltage Level, L = Low Voltage Level

nA

nB

2