8-1
Data sheet acquired from Harris Semiconductor
SCHS267
Features
• Buffered Inputs
• Typical Propagation Delay: 6.8ns at V
CC
= 5V,
T
A
= 25oC, CL = 50pF (FCT843A)
• CD74FCT843A
- Noninverting
• CD74FCT844A
- Inverting
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 48mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V
CC
= 5V
• Controlled Output Edge Rates
• Input/Output Isolation to V
CC
• BiCMOS Technology with Low Quiescent Power
Pinouts
Ordering Information
PART NUMBER
TEMP.
RANGE (oC) PACKAGE
PKG.
NO.
CD74FCT844AEN 0 to 70 24 Ld PDIP E24.3
CD74FCT843AM 0 to 70 24 Ld SOIC M24.3
NOTE: When ordering the suffix M package, use the entire part
number. Add the suffix 96 to obtain the variant in the tape and reel.
CD74FCT843A
(SOIC)
TOP VIEW
CD74FCT844A
(PDIP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
Y1
Y3
Y4
Y6
Y8
PRE
LE
Y0
Y5
Y7
Y2
1
2
3
4
5
6
7
8
9
10
11
12
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
CLR
GND
16
17
18
19
20
21
22
23
24
15
14
13
VCC
Y1
Y3
Y4
Y6
Y8
PRE
LE
Y0
Y5
Y7
Y2
January 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright
© Harris Corporation 1997
CD74FCT843A,
CD74FCT844A
BiCMOS FCT Interface Logic,
9-Bit Transparent Latc hes, Three-State
File Number 2396.2
NOT RECOMMENDED
FOR NEW DESIGNS
Use CMOS Technology
8-2
Functional Diagram
TRUTH TABLE (Note 1)
INPUTS OUTPUTS
FUNCTION
CLR PRE OE LE
843A
Dn
844A
Dn Yn
H H H X X X Z High Z
H H H L X X Z Latched (High Z)
HHLHLHLTransparent
H H L H H L H Transparent
H H L L X X NC Latched
H L L X X X H Preset
L H L X X X L Clear
L L L X X X H Preset
L H H L X X Z Latched (High Z)
HLHLXXZLatched (High Z)
NOTE:
1. H= HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
NC = No Change
Z = High Impedance
2
3
4
5
6
7
8
9
23
22
21
20
19
18
17
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
D0
D1
D2
D3
D4
D5
D6
D7
13
GND = PIN 12
V
CC
= PIN 24
14
LE
PRE
16
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
843A 844A
10
D8
15
Y8
Y8
111
CLR
OE
CD74FCT843A, CD74FCT844A
8-3
IEC Logic Symbol
CD74FCT843A CD74FCT844A
EN
1
2
3
4
5
6
7
8
9
S
13
1D
10
23
22
21
20
19
18
17
16
15
11
14
C1
R
EN
1
2
3
4
5
6
7
8
9
S
13
1D
10
23
22
21
20
19
18
17
16
15
11
14
C1
R
CD74FCT843A, CD74FCT844A
8-4
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Diode Current, IIK (For VI < -0.5V). . . . . . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA
DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237mA
DC Ground Current (I
GND
). . . . . . . . . . . . . . . . . . . . . . . . . . .453mA
Operating Conditions
Operating Temperature Range, TA. . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V
CC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . .300oC
(SOIC-Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0
o
C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V
PARAMETER SYMBOL
TEST CONDITIONS
V
CC
(V)
AMBIENT TEMPERATURE (TA)
UNITS
25oC0
o
C TO 70oC
VI (V) IO (mA) MIN MAX MIN MAX
High Level Input Voltage V
IH
4.75 to
5.25
2-2-V
Low Level Input Voltage V
IL
4.75 to
5.25
- 0.8 - 0.8 V
High Level Output Voltage V
OH
VIH or V
IL
-15 Min 2.4 - 2.4 - V
Low Level Output Voltage V
OL
VIH or V
IL
48 Min - 0.55 - 0.55 V
High Level Input Current I
IH
V
CC
Max - 0.1 - 1 µA
Low Level Input Current I
IL
GND Max - -0.1 - -1 µA
Three-State Leakage Current I
OZH
V
CC
Max - 0.5 - 10 µA
I
OZL
GND Max - -0.5 - -10 µA
Input Clamp Voltage V
IK
VCC or
GND
-18 Min - -1.2 - -1.2 V
Short Circuit Output Current
(Note 3)
I
OS
VO = 0
VCC or
GND
Max -75 - -75 - mA
Quiescent Supply Current,
MSI
I
CC
VCC or
GND
0 Max - 8 - 80 µA
Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load
∆I
CC
3.4V
(Note 4)
Max - 1.6 - 1.6 mA
NOTES:
3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
4. Inputs that are not measured are at VCC or GND.
5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max. @ 70oC.
CD74FCT843A, CD74FCT844A
8-5
Switching Specifications Over Operating Range FCT Series t
r
, tf = 2.5ns, CL = 50pF, RL (Figure 1)
PARAMETER SYMBOL V
CC
(V)
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
Propagation Delays
Data to Outputs CD74FCT843A t
PLH
, t
PHL
5
(Note 6)
6.8 1.5 9 ns
CD74FCT844A t
PLH
, t
PHL
5 7.5 1.5 10 ns
LE to Outputs t
PLH
, t
PHL
5 9 1.5 12 ns
PRE to Outputs t
PLH
5 9 1.5 12 ns
CLR to Outputs t
PHL
5 9.8 1.5 13 ns
Output Enable Times t
PZL
, t
PZH
- 10.5 1.5 14 ns
Output Disable Times t
PLZ
, t
PHZ
- 6 1.5 8 ns
Power Dissipation Capacitance C
PD
(Note 7)
----pF
Minimum (Valley) V
OHV
During Switching of
Other Outputs (Output Under Test Not Switching)
V
OHV
5 0.5 - - V
Maximum (Peak) V
OLP
During Switching of
Other Outputs (Output Under Test Not Switching)
V
OLP
51-- V
Input Capacitance C
I
---10pF
Three-State Output Capacitance C
O
---15pF
NOTES:
6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V.
7. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(V
CC
2
fI CPD + V
O
2
fOCL + VCC∆ICC D) where:
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
Prerequisite for Switching
PARAMETER SYMBOL VCC (V)
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
Setup Time, Data to LE t
SU
5
(Note 8)
- 2.5 - ns
Hold Time, Data to LE t
H
5 - 2.5 - ns
LE Pulse Width t
W
5-4-ns
PRE, CLR Pulse Width t
W
5-8-ns
PRE, CLR Recovery Time t
REC
5 - 14 - ns
NOTE:
8. Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
Test Circuits and Waveforms
NOTE:
9. Pulse Generator for All Pulses: Rate ≤1.0MHz; Z
≤ 50Ω;
3V
0
DUT
PULSE Z
O
GEN
7V
500Ω
50pF
500Ω
V
CC
R
T
RT = Z
O
V
0
C
L
R
L
R
L
V
I
tr, tf = 2.5ns
(NOTE 9)
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
, Open Drain Closed
t
PHZ
, t
PZH
, t
PLH
, t
PHL
Open
DEFINITIONS:
C
L
= Load capacitance, includes jig and probe
capacitance.
RT= Termination resistance, should be equal to Z
OUT
of
the Pulse Generator.
CD74FCT843A, CD74FCT844A
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERT AIN APPLICATIONS USING SEMICONDUCT OR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICA TIONS IS UNDERST OOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 1999, Texas Instruments Incorporated
Loading...