CD74FCT823A,
Data sheet acquired from Harris Semiconductor
SCHS265
January 1997
NOT RECOMMENDED
Features
• Buffered Inputs
• Typical Propagation Delay: 7.5ns at V
T
= 25oC, CL = 50pF
A
• Positive Edge Triggered
• CD74FCT824A
- Inverting
• CD74FCT823A
- Noninverting
• SCR Latchup Resistant BiCMOS Process and
FOR NEW DESIGNS
Use CMOS Technology
CC
Pinout
CD74FCT823A
(PDIP)
TOP VIEW
= 5V,
CD74FCT824A
BiCMOS FCT Interface Logic,
9-Bit D-Type Flip-Flops, Three-State
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 48mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V
• Controlled Output Edge Rates
• Input/Output Isolation to V
CC
• BiCMOS Technology with Low Quiescent Power
Ordering Information
TEMP.
PART NUMBER
CD74FCT823AEN 0 to 70 24 Ld PDIP E24.3
CD74FCT824AEN 0 to 70 24 Ld PDIP E24.3
RANGE (oC) PACKAGE
CD74FCT824A
(PDIP)
TOP VIEW
CC
= 5V
PKG.
NO.
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
VCC
Q0
23
22
Q1
Q2
21
20
Q3
19
Q4
Q5
18
17
Q6
16
Q7
15
Q8
14
CE
CP
13
OE
D0
D1
D2
D3
D4
D5
D6
D7
D8
MR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
VCC
23
Q0
22
Q1
Q2
21
20
Q3
19
Q4
18
Q5
17
Q6
16
Q7
15
Q8
14
CE
CP
13
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright
© Harris Corporation 1997
8-1
File Number 2389.2
Functional Diagram
H
H
H
L
H
L
H
H
L
L
NOTE:
1. H= HIGH Voltage Level
L = LOW Voltage Level
NC = No Change
↑ = LOW to HIGH Transition
X = Don’t Care
Z = HIGH Impedance
CD74FCT823A, CD74FCT824A
23
22
21
20
19
18
17
16
15
1311
NC
D8
CE
OE
2
3
4
5
6
7
8
9
10
14
1
D0
D1
D2
D3
D4
D5
D6
D7
TRUTH TABLE (Note 1)
INPUTS Q OUTPUTS
X
X
L
L
H
H
H
H
H
H
L
L
X
X
H
H
L
L
L
L
L
H
X
X
X
X
L
H
L
H
↑
↑
X
X
X
X
↑
↑
↑
↑
823A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
CP
MR
824A
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
GND = PIN 12
= PIN 24
V
CC
FUNCTIONOE MR CE D CP CD74FCT823A CD74FCT824A
Z
Z
Z
L
Z
Z
High Z
Z
Z
Reset
L
Z
Hold
NC
Z
Z
L
H
Z
Load
Z
H
L
IEC Logic Symbol
CD74FCT823A CD74FCT824A
1
11
14
13
2
3
4
5
6
7
8
9
10
EN
R
G1
>1C2
2D
1
EN
11
14
13
23
22
21
20
19
18
17
16
15
10
R
G1
>1C2
2
2D
3
4
5
6
7
8
9
23
22
21
20
19
18
17
16
15
8-2
CD74FCT823A, CD74FCT824A
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Diode Current, IIK (For VI < -0.5V). . . . . . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA
DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234mA
DC Ground Current (I
). . . . . . . . . . . . . . . . . . . . . . . . . . .453mA
GND
Operating Conditions
Operating Temperature Range, TA. . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
2. θJA is measured with the component mounted on an evaluation PC board in free air.
Thermal Resistance (Typical, Note 2) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
CC
CC
Electrical Specifications Commercial Temperature Range 0
o
C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V
AMBIENT TEMPERATURE (TA)
o
C TO 70oC
UNITS
PARAMETER SYMBOL
High Level Input Voltage V
Low Level Input Voltage V
High Level Output Voltage V
Low Level Output Voltage V
High Level Input Current I
Low Level Input Current I
Three-State Leakage Current I
Input Clamp Voltage V
OH
OL
IH
IL
OZH
I
OZL
TEST CONDITIONS
V
VI (V) IO (mA) MIN MAX MIN MAX
IH
IL
VIH or V
VIH or V
V
CC
-15 Min 2.4 - 2.4 - V
IL
48 Min - 0.55 - 0.55 V
IL
(V)
CC
4.75 to 5.25 2-2-V
4.75 to 5.25 - 0.8 - 0.8 V
Max - 0.1 - 1 µA
25oC0
GND Max - -0.1 - -1 µA
V
CC
Max - 0.5 - 10 µA
GND Max - -0.5 - -10 µA
IK
VCC or
-18 Min - -1.2 - -1.2 V
GND
Short Circuit Output Current
(Note 3)
I
OS
VO = 0
Max -75 - -75 - mA
VCC or
GND
Quiescent Supply Current,
MSI
Additional Quiescent Supply
Current per Input Pin
I
CC
VCC or
0 Max - 8 - 80 µA
GND
∆I
CC
3.4V
Max - 1.6 - 1.6 mA
(Note 4)
TTL Inputs High, 1 Unit Load
NOTES:
3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
4. Inputs that are not measured are at VCC or GND.
5. FCT Input Loading:Allinputs are 1 unit load. Unitload is ∆ICClimit specified inElectricalSpecifications table, e.g., 1.6mA Max. at70oC.
8-3
CD74FCT823A, CD74FCT824A
Switching Specifications Over Operating Range FCT Series t
PARAMETER SYMBOL V
, tf = 2.5ns, CL = 50pF, RL (Figure 1)
r
(V)
CC
Propagation Delays (Note 6)
Clock to Q CD74FCT823A t
Clock to Q CD74FCT824A t
MR to Q t
Output Enable to Q CD74FCT823A t
Output Disable to Q CD74FCT823A t
Output Enable to Q CD74FCT824A t
Output Disable to Q CD74FCT824A t
Power Dissipation Capacitance C
PLH
PLH
PZL
PLZ
PZL
PLZ
, t
, t
PHL
, t
, t
, t
, t
PD
PHL
PHL
PZH
PHZ
PZH
PHZ
5 7.5 1.5 10 ns
5 7.5 1.5 10 ns
5 10.5 1.5 14 ns
5 9 1.5 12 ns
5 6 1.5 8 ns
5 9 1.5 12 ns
5 6 1.5 8 ns
----pF
(Note 7)
Minimum (Valley) V
During Switching of
OHV
V
OHV
5 0.5 --V
Other Outputs (Output Under Test Not Switching)
Maximum (Peak) V
During Switching of
OLP
V
OLP
51- -V
Other Outputs (Output Under Test Not Switching)
Input Capacitance C
Three-State Output Capacitance C
I
O
---10pF
---15pF
NOTES:
6. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V.
7. CPD, measured per flip-flop,is used to determine the dynamic powerconsumption.
PD (per package) = VCC ICC + Σ(V
2
fI CPD + V
CC
2
fOCL + VCC∆ICC D) where:
O
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
Prerequisite for Switching
PARAMETER SYMBOL VCC (V)
Maximum Clock Frequency f
Master Reset Recovery Time t
Setup Time, Data to Clock, CE to Clock t
Hold Time - Data, CE t
Pulse Width - Clock, MR t
NOTE:
8. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
MAX
REC
SU
H
W
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
5
- 70 - MHz
(Note 8)
5-7-ns
5-4-ns
5-2-ns
5-7-ns
8-4
CD74FCT823A, CD74FCT824A
Test Circuits and Waveforms
V
tr, tf = 2.5ns
V
3V
(NOTE 9)
PULSE Z
GEN
RT = Z
I
0
O
O
R
NOTE:
9. Pulse Generator forAll Pulses: Rate ≤ 1.0MHz; Z
tf, tr≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
CC
V
DUT
T
0
50pF
SWITCH POSITION
7V
500Ω
R
L
C
500Ω
L
R
L
DEFINITIONS:
TEST SWITCH
t
, t
PLZ
t
PHZ
, Open Drain Closed
PZL
, t
, t
PLH
, t
PHL
PZH
C
= Load capacitance, includes jig and probe
L
Open
capacitance.
OUT
≤ 50Ω;
RT= Termination resistance,should be equalto Z
the Pulse Generator.
VIN = 0V to 3V.
OUT
of
Input: tr=tf= 2.5ns (10% to 90%),unlessotherwise specified
DAT A
INPUT
TIMING
INPUT
ASYNCHRONOUS CONTROL
SYNCHRONOUS CONTROL
PRESET CLEAR
CLOCK ENABLE
ETC.
t
SH
t
REM
t
SH
t
H
t
H
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
LOW-HIGH-LOW
HIGH-LOW-HIGH
PULSE
PULSE
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING FIGURE 3. PULSE WIDTH
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH
ENABLE DISABLE
t
PZL
SWITCH
CLOSED
t
PZH
SWITCH
OPEN
3.5V
1.5V
1.5V
0V
t
t
PHZ
PLZ
0.3V
0.3V
3V
1.5V
0V
3.5V
V
OL
V
OH
0V
SAME PHASE
INPUT TRANSITION
OUTPUT
OPPOSITE PHASE
INPUT TRANSITION
FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY
t
PLH
t
PLH
1.5V
t
W
1.5V
3V
1.5V
t
t
PHL
PHL
0V
V
OH
1.5V
V
OL
3V
1.5V
0V
8-5
Test Circuits and Waveforms
OTHER
OUTPUTS
OUTPUT
UNDER
TEST
(Continued)
V
V
V
V
V
V
OH
OL
OH
OHV
OLP
OL
NOTES:
10. V
is measured with respect to a ground reference near the output under test. V
OLP
is measured with respect to VOH.
OHV
11. Input pulses have the following characteristics:
PRR≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.
12. R.F. fixture with 700MHz design rulesrequired.IC should be soldered into test board and bypassed with 0.1µF capacitor. Scopeand
probes require 700MHz bandwidth.
FIGURE 6. SIMUL TANEOUS SWITCHING TRANSIENT WAVEFORMS
8-6
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