8-67
Data sheet acquired from Harris Semiconductor
SCHS261
Features
• Buffered Inputs
• Typical Propagation Delay: 6.8ns at V
CC
= 5V,
T
A
= 25oC, CL = 50pF
• Noninverting
• SCR Latchup Resistant BiCMOS Process and
Circuit Design
• Speed of Bipolar FAST™/AS/S
• 64mA Output Sink Current
• Output Voltage Swing Limited to 3.7V at V
CC
= 5V
• Controlled Output Edge Rates
• Input/Output Isolation to V
CC
• BiCMOS Technology with Low Quiescent Power
Description
The CD74FCT646 three-state octal bus transceiver/register
uses a small geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors that
limits the output HIGH level to two diode drops below V
CC
.
This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
V
CC
bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
64 milliamperes.
This device is a bus transceiver with D-Type flip-flops which
act as internal storage registers on the LOW to HIGH transition of either CAB or CBA clock inputs. Output Enable (
OE)
and Direction (DIR) inputs control the transceiver functions.
Data present at the high impedance output can be stored in
either register or both but only one of the two buses can be
enabled as outputs at any one time. The Select controls
(SAB and SBA) can multiplex stored and transparent (real
time) data. The Direction control determines which data bus
will receive data when the Output Enable(
OE) is LOW. In the
high impedance mode (Output Enable HIGH), A data can be
stored in one register and B data can be stored in the other
register. The clocks are not gated with the Direction (DIR)
and Output Enable (
OE) terminals; data at the A or B termi-
nals can be clocked into the storage flip-flops at any time.
Pinout
Ordering Information
PART NUMBER
TEMP.
RANGE (oC) PACKAGE
PKG.
NO.
CD74FCT646EN 0 to 70 24 Ld PDIP E24.3
CD74FCT646M 0 to 70 24 Ld SOIC M24.3
CD74FCT646SM 0 to 70 24 Ld SSOP M24.209
NOTE: When ordering the suffix M and SM packages, use the entire
part number .Add thesuffix 96to obtainthevariant inthe tapeand reel.
CD74FCT646
(PDIP, SOIC, SSOP)
TOP VIEW
1
2
3
4
5
6
7
8
9
10
11
12
CAB
A0
A1
A2
A3
A4
A5
A6
A7
GND
16
17
18
19
20
21
22
23
24
15
14
13
V
CC
B1
B3
B4
B6
B0
B5
B7
B2
SAB
DIR
CBA
SBA
OE
January 1997
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.
Copyright
© Harris Corporation 1997
CD74FCT646
BiCMOS FCT Interface Logic,
Octal Bus Transceiver/Register, Three-State
NO
T RECOMMENDED
FOR NEW DESIGNS
Use CMOS T
echnology
File Number 2393.2
8-68
Functional Diagram
TRUTH TABLE (Note 1)
INPUTS DATA I/O (Note 2) OPERATION OR FUNCTION
OE DIR CAB CBA SAB SBA A0 THRU A7 B0 THRU B7 CD74FCT646
X
X
X
X
↑
X
X
↑
X
X
XXInput
Not Specified
Not Specified
Input
Store A, B Unspecified
Store B, A Unspecified
H
H
X
X↑H or L↑H or LXX
XXInput Input Store A and B Data
Isolation, Hold Storage
L
L
L
L
X
XXH or LXX
LHOutput Input Real Time B Data to A Bus
Stored B Data to A Bus
L
L
H
HXH or LXX
L
H
XXInput Output Real Time A Data to B Bus
Stored A Data to B Bus
NOTES:
1. H= HIGH Voltage Level
L = LOW Voltage Level
↑ = Transition from Low to High
X = Immaterial
2. Thedataoutput functions may be enabled or disabled by various signals at the OE and DIR inputs. Data input functionsarealwaysenabled, i.e., data atthebus pins will be stored on every lowto high transition of the clock inputs. To prevent excess currents in the high Z
modes, all I/O terminals should be terminated with 10kΩ resistors.
4
5
6
7
8
9
10
11
20
19
18
17
16
15
14
13
B0
B1
B2
B3
B4
B5
B6
B7
A0
A1
A2
A3
A4
A5
A6
A7
B DATA PORTA DATA PORT
OE
DIR
CAB CLOCK
CBA CLOCK
21
3
1
23
2
22
SAB SOURCE
SBA SOURCE
DATA SOURCE
SELECTION
INPUTS
FLIP-FLOP
CLOCKS
GND = PIN 12
V
CC
= PIN 24
CD74FCT646
8-69
IEC Logic Symbol
CD74FCT646
G3
3EN1
G6
5D
4D
21
22
2
23
1
6
7
8
9
10
4
5
18
17
16
15
14
13
19
20
11
7
7
2
>C4
>C5
1
6
6
≥1
≥1
3EN2
3
G7
CD74FCT646
8-70
Absolute Maximum Ratings Thermal Information
DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V
DC Diode Current, IIK (For VI < -0.5V). . . . . . . . . . . . . . . . . . -20mA
DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA
DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA
DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA
DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140mA
DC Ground Current (I
GND
). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA
Operating Conditions
Operating Temperature Range, TA. . . . . . . . . . . . . . . . .0oC to 70oC
Supply Voltage Range, VCC . . . . . . . . . . . . . . . . . . .4.75V to 5.25V
DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V
CC
DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V
CC
Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V
Thermal Resistance (Typical, Note 3) θJA (oC/W)
PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC
(SOIC and SSOP-Lead Tips Only)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE:
3. θJA is measured with the component mounted on an evaluation PC board in free air.
Electrical Specifications Commercial Temperature Range 0
o
C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 6)
PARAMETER SYMBOL
TEST CONDITIONS
VCC (V)
AMBIENT TEMPERATURE (TA)
UNITS
25oC0
o
C TO 70oC
VI (V) IO (mA) MIN MAX MIN MAX
High Level Input Voltage V
IH
4.75 to 5.25 2 - 2 - V
Low Level Input Voltage V
IL
4.75 to 5.25 - 0.8 - 0.8 V
High Level Output Voltage V
OH
VIH or V
IL
-15 Min 2.4 - 2.4 - V
Low Level Output Voltage V
OL
VIH or V
IL
64 Min - 0.55 - 0.55 V
High Level Input Current I
IH
V
CC
Max - 0.1 - 1 µA
Low Level Input Current I
IL
GND Max - -0.1 - -1 µA
Three-State Leakage Current I
OZH
V
CC
Max - 0.5 - 10 µA
I
OZL
GND Max - -0.5 - -10 µA
Input Clamp Voltage V
IK
VCC or
GND
-18 Min - -1.2 - -1.2 V
Short Circuit Output Current
(Note 4)
I
OS
VO = 0
VCC or
GND
Max -60 - -60 - mA
Quiescent Supply Current,
MSI
I
CC
VCC or
GND
0 Max - 8 - 80 µA
Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load
∆I
CC
3.4V
(Note 5)
Max - 1.6 - 1.6 mA
NOTES:
4. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.
5. Inputs that are not measured are at VCC or GND.
6. FCTInput Loading: All inputs are 1 unit load. Unit load is ∆ICClimit specified in Electrical Specifications table, e.g., 1.6mA Max. at 70oC.
CD74FCT646
8-71
CD74FCT646
Switching Specifications Over Operating Range FCT Series t
r
, tf = 2.5ns, CL = 50pF, RL (Figure 1) (Note 7)
PARAMETER SYMBOL VCC (V)
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
Propagation Delays (Note 8)
Store An → Bn, Store Bn → An, An → Bn, Bn → An t
PLH
, t
PHL
5 6.8 2 9 ns
Select to Data t
PLH
, t
PHL
5 8.3 2 11 ns
Output Enable to Output t
PZL
, t
PZH
5 10.5 2 14 ns
Output Disable to Output t
PLZ
, t
PHZ
5 6.8 2 9 ns
Power Dissipation Capacitance C
PD
(Note 8)
----pF
Minimum (Valley) V
OHV
During Switching of
Other Outputs (Output Under Test Not Switching)
V
OHV
5 0.5 - - V
Maximum (Peak) V
OLP
During Switching of
Other Outputs (Output Under Test Not Switching)
V
OLP
51- - V
Input Capacitance C
I
---10pF
Input/Output Capacitance C
I/O
---15pF
NOTES:
7. 5V: Minimum is at 5.25V for 0oC to 70oC, Maximum is at 4.75V for 0oC to 70oC, Typical is at 5V.
8. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(V
CC
2
fI CPD + V
O
2
fOCL + VCC∆ICC D) where:
VCC = supply voltage
∆ICC = flow through current x unit load
CL = output load capacitance
D = duty cycle of input high
fO = output frequency
fI = input frequency
Prerequisite For Switching
PARAMETER SYMBOL VCC (V)
25oC0
o
C TO 70oC
UNITSTYP MIN MAX
Maximum Frequency f
MAX
5
(Note 9)
-85-ns
Data to Clock Setup Time t
SU
5-4-ns
Data to Clock Hold Time t
H
5-2-ns
Clock Pulse Width t
W
5-6-ns
NOTE:
9. 5V: Minimum is at 4.75V for 0oC to 70oC, Typical is at 5V.
8-72
Test Circuits and Waveforms
NOTE:
10. PulseGenerator for All Pulses: Rate ≤ 1.0MHz; Z
OUT
≤ 50Ω;
tf, tr≤ 2.5ns.
FIGURE 1. TEST CIRCUIT
FIGURE 2. SETUP, HOLD, AND RELEASE TIMING FIGURE 3. PULSE WIDTH
FIGURE 4. ENABLE AND DISABLE TIMING FIGURE 5. PROPAGATION DELAY
3V
0
DUT
PULSE Z
O
GEN
7V
500Ω
50pF
500Ω
V
CC
R
T
RT = Z
O
V
0
C
L
R
L
R
L
V
I
tr, tf = 2.5ns
(NOTE 10)
SWITCH POSITION
TEST SWITCH
t
PLZ
, t
PZL
, Open Drain Closed
t
PHZ
, t
PZH
, t
PLH
, t
PHL
Open
DEFINITIONS:
CL = Load capacitance, includes jig and probe
capacitance.
RT= Terminationresistance, should be equal to Z
OUT
of
the Pulse Generator.
VIN = 0V to 3V.
Input: tr=tf= 2.5ns (10% to 90%), unless otherwise specified
ASYNCHRONOUS CONTROL
t
H
t
SH
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
3V
1.5V
0V
t
H
t
SH
PRESET CLEAR
CLOCK ENABLE
ETC.
SYNCHRONOUS CONTROL
t
REM
DAT A
INPUT
TIMING
INPUT
t
W
LOW-HIGH-LOW
PULSE
HIGH-LOW-HIGH
PULSE
1.5V
1.5V
3V
1.5V
0V
CONTROL INPUT
OUTPUT
NORMALLY LOW
OUTPUT
NORMALLY HIGH
SWITCH
OPEN
t
PZL
3.5V
1.5V
1.5V
0V
t
PLZ
t
PHZ
t
PZH
0V
3.5V
0.3V
0.3V
V
OL
V
OH
SWITCH
CLOSED
ENABLE DISABLE
1.5V
3V
0V
1.5V
3V
0V
t
PLH
SAME PHASE
INPUT TRANSITION
t
PHL
t
PLH
t
PHL
OPPOSITE PHASE
INPUT TRANSITION
OUTPUT
1.5V
V
OH
V
OL
8-73
NOTES:
11. V
OLP
is measured with respect to a ground reference near the output under test. V
OHV
is measured with respect to VOH.
12. Input pulses have the following characteristics:
PRR≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.
13. R.F.fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.
FIGURE 6. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS
Test Circuits and Waveforms
(Continued)
OTHER
OUTPUTS
OUTPUT
UNDER
TEST
V
OH
V
OL
V
OH
V
OHV
V
OLP
V
OL
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