Texas Instruments CD74FCT574SM, CD74FCT574M96, CD74FCT574M, CD74FCT574E, CD74FCT564M Datasheet

8-1

Data sheet acquired from Harris Semiconductor
SCHS259

Features

• Buffered Inputs

• Typical Propagation Delay: 5.6ns at V

CC

= 5V,

T

A

= 25oC

• Positive Edge Triggered

• CD74FCT564

- Inverting

• CD74FCT574

- Noninverting

• SCR Latchup Resistant BiCMOS Process and
Circuit Design

• Speed of Bipolar FAST™/AS/S

• 48mA Output Sink Current

• Output Voltage Swing Limited to 3.7V at V

CC

= 5V

• Controlled Output Edge Rates

• Input/Output Isolation to V

CC

• BiCMOS Technology with Low Quiescent Power

Description

The CD74FCT564 and CD74FCT574 are octal D-Type,
three-state, positive edge triggered flip-flops which use a
small geometry BiCMOS technology. The output stage is a
combination of bipolar and CMOS transistors that limits the
output HIGH level totwo diode drops below V

CC

. This result­ant lowering of output swing (0V to 3.7V) reduces power bus
ringing (a source of EMI) and minimizes V

CC

bounce and
ground bounce and their effects during simultaneous output
switching. The output configuration also enhances switching
speed and is capable of sinking 48 milliamperes.

The eight flip-flops enter data into their registers on the LOW
to HIGH transition of the clock (CP). The Output Enable (

OE)
controls the three state outputs and is independent of the
register operation. When the Output Enable (

OE) is HIGH,
the outputs are in the high impedance state. The
CD74FCT564 and CD74FCT574 share the same configura­tions; the CD74FCT564, however, has inverted outputs and
the CD74FCT574 has noninverted outputs.

Pinouts

Ordering Information

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74FCT564E 0 to 70 20 Ld PDIP E20.3
CD74FCT574E 0 to 70 20 Ld PDIP E20.3
CD74FCT564M 0 to 70 20 Ld SOIC M20.3
CD74FCT574M 0 to 70 20 Ld SOIC M20.3
CD74FCT574SM 0 to 70 20 Ld SSOP M20.209

NOTE: Whenordering the suffix M and SM packages, use the entire
part number.Addthesuffix96to obtain the variant in the tape and reel.

CD74FCT564

(PDIP, SOIC, SSOP)

TOP VIEW

CD74FCT574

(PDIP, SOIC, SSOP)

TOP VIEW

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

OE

D0
D1
D2
D3
D4

D6

D5

D7

GND

V

CC

Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP

Q0

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

OE

D0
D1
D2
D3
D4

D6

D5

D7

GND

V

CC

Q1
Q2
Q3
Q4
Q5
Q6
Q7
CP

Q0

January 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1997

CD74FCT564,

CD74FCT574

BiCMOS FCT Interface Logic,

Octal D-Type Flip-Flops, Three-State

File Number 2295.2

NOT RECOMMENDED

FOR NEW DESIGNS

Use CMOS Technology

8-2

Functional Diagram

IEC Logic Symbols

2

3

4

5

6

7

8

9

19

18

17

16

15

14

13

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

D0

D1

D2

D3

D4

D5

D6

D7

1

GND = PIN 10
V

CC

= PIN 20

11

OE
CP

12

Q0

Q1

Q2

Q3

Q4

Q5

Q6

Q7

CD74FCT574 CD74FCT564

TRUTH TABLE (NOTE 1)

INPUTS

OUTPUTS

CD74FCT564 CD74FCT574

OE CP DN QN QN

L ↑ HL H
L↑LH L
LLX Qo Qo
HXX Z Z

NOTE:

1. H = High Level (Steady State)
L = Low Level (Steady State)
X = Don't Care
↑ = Transition from low to high level
Qo = The level of Q before the indicated steady state input
conditions were established.
Z = HIGH Impedance

CD74FCT564 CD74FCT574

19
18
17
16

EN

1

2

3

4
5

15
14
13
12

6

7

8
9

>C1

11

1D

19
18
17
16

EN

1

2

3

4
5

15
14
13
12

6

7

8
9

>C1

11

1D

CD74FCT564, CD74FCT574