Texas Instruments CD74FCT541SM, CD74FCT541M96, CD74FCT541M, CD74FCT541E, CD74FCT540M96 Datasheet

8-1

Data sheet acquired from Harris Semiconductor
SCHS257

Features

• Buffered Inputs

• Typical Propagation Delay: 6.4ns at V

CC

= 5V,

T

A

= 25oC, CL = 50pF

• CD74FCT540

- Inverting

• CD74FCT541

- Noninverting

• SCR Latchup Resistant BiCMOS Process and
Circuit Design

• Speed of Bipolar FAST™/AS/S

• 64mA Output Sink Current

• Output Voltage Swing Limited to 3.7V at V

CC

= 5V

• Controlled Output Edge Rates

• Input/Output Isolation to V

CC

• BiCMOS Technology with Low Quiescent Power

Description

The CD74FCT540 and CD74FCT541 octal buffers/linedrivers
use a small geometry BiCMOS technology. The output
stage is a combination of bipolar and CMOS transistors
that limits the output HIGH level to two diode drops below
V

CC

. This resultant lowering of output swing (0V to 3.7V)
reduces power bus ringing (a source of EMI) and minimizes
V

CC

bounce and ground bounce and their effects during
simultaneous output switching. The output configuration
also enhances switching speed and is capable of sinking
64 milliamperes.

The CD74FCT540 is a three-state buffer having two active
LOW output enables. The CD74FCT541 is a noninverting
three state buffer having two active LOW output enables.

Ordering Information

Pinouts

PART NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74FCT540E 0 to 70 20 Ld PDIP E20.3
CD74FCT541E 0 to 70 20 Ld PDIP E20.3
CD74FCT540M 0 to 70 20 Ld SOIC M20.3
CD74FCT541M 0 to 70 20 Ld SOIC M20.3
CD74FCT541SM 0 to 70 20 Ld SSOP M20.209

NOTE: When ordering the suffix M and SM packages, use the entire
part number.Addthe suffix 96 to obtain thev ariantin the tape and reel.

CD74FCT540

(PDIP, SOIC)

TOP VIEW

CD74FCT541

(PDIP, SOIC, SSOP)

TOP VIEW

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

OE1

A0
A1
A2
A3
A4

A6

A5

A7

GND

V

CC

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

OE2

11

12

13

14

15

16

17

18

20
19

10

9

8

7

6

5

4

3

2

1

OE1

A0
A1
A2
A3
A4

A6

A5

A7

GND

V

CC

Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7

OE2

January 1997

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1997

CD74FCT540,

CD74FCT541

BiCMOS FCT Interface Logic,

Octal Buffers/Line Drivers, Three-State

NOT RECOMMENDED

FOR NEW DESIGNS

Use CMOS Technology

File Number 2383.2

8-2

Functional Diagram

IEC Logic Symbol

TRUTH TABLE (Note 1)

INPUTS OUTPUTS

OE1 OE2 A

n

CD74FCT540 CD74FCT541

LLHLH
HXXZZ
XHXZZ
LLLHL

NOTE:

1. H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = HIGH Impedance

2

3

4

5

6

7

8

9

18

17

16

15

14

13

12

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

A0

A1

A2

A3

A0

A1

A2

A3

1

GND = PIN 10
V

CC

= PIN 20

19

OE1
OE2

11

Y0

Y1

Y2

Y3

Y4

Y5

Y6

Y7

541 540

CD74FCT540 CD74FCT541

18
17
16
15

EN

1

2

3

4
5

14
13
12
11

6

7

8
9

19

18
17
16
15

EN

1

2

3

4
5

14
13
12
11

6

7

8
9

19

CD74FCT540, CD74FCT541

8-3

Absolute Maximum Ratings Thermal Information

DC Supply Voltage (VCC). . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, IIK (For VI < -0.5V) . . . . . . . . . . . . . -20mA

DC Output Diode Current, IOK (for VO < -0.5V) . . . . . . . . . . . -50mA

DC Output Sink Current per Output Pin, IO . . . . . . . . . . . . . . .70mA

DC Output Source Current per Output Pin, IO. . . . . . . . . . . . -30mA

DC VCC Current (ICC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .140mA

DC Ground Current (I

GND

). . . . . . . . . . . . . . . . . . . . . . . . . . .528mA

Operating Conditions

Operating Temperature Range (TA) . . . . . . . . . . . . . . . .0oC to 70oC

Supply Voltage Range, VCC. . . . . . . . . . . . . . . . . . . .4.75V to 5.25V

DC Input Voltage, VI. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to V

CC

DC Output Voltage, VO. . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to ≤ V

CC

Input Rise and Fall Slew Rate, dt/dv. . . . . . . . . . . . . . . . 0 to 10ns/V

Thermal Resistance (Typical, Note 2) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130

Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC and SSOP-Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:

2. θJA is measured with the component mounted on an evaluation PC board in free air.

Electrical Specifications Commercial Temperature Range 0

o

C to 70oC, VCC Max = 5.25V, VCC Min = 4.75V (Note 5)

PARAMETER SYMBOL

TEST CONDITIONS

V

CC

(V)

AMBIENT TEMPERATURE (TA)

UNITS

25oC0

o

C TO 70oC

VI (V) IO (mA) MIN MAX MIN MAX

High Level Input Voltage V

IH

4.75 to 5.25 2 - 2 - V

Low Level Input Voltage V

IL

4.75 to 5.25 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-15 Min 2.4 - 2.4 - V

Low Level Output Voltage V

OL

VIH or V

IL

64 Min - 0.55 - 0.55 V

High Level Input Current I

IH

V

CC

Max - 0.1 - 1 µA

Low Level Input Current I

IL

GND Max - -0.1 - -1 µA

Three State Leakage Current I

OZH

V

CC

Max - 0.5 - 10 µA

I

OZL

GND Max - -0.5 - -10 µA

Input Clamp Voltage V

IK

VCC or

GND

-18 Min - -1.2 - -1.2 V

Short Circuit Output Current
(Note 3)

I

OS

VO = 0
VCC or

GND

Max -60 - -60 - mA

Quiescent Supply Current,
MSI

I

CC

VCC or

GND

0 Max - 8 - 80 µA

Additional Quiescent Supply
Current per Input Pin
TTL Inputs High, 1 Unit Load

∆I

CC

3.4V

(Note 4)

Max - 1.6 - 1.6 mA

NOTES:

3. Not more than one output should be shorted at one time. Test duration should not exceed 100ms.

4. Inputs that are not measured are at VCC or GND.

5. FCT Input Loading: All inputs are 1 unit load. Unit load is ∆ICC limit specified in Static Characteristics Chart, e.g., 1.6mA Max. @ 70oC.

CD74FCT540, CD74FCT541

8-4

Switching Specifications Over Operating Range FCT Series t

r

, tf = 2.5ns, CL = 50pF, RL (Figure 3) (Note 6)

PARAMETER SYMBOL V

CC

(V)

25oC0

o

C TO 70oC

UNITSTYP MIN MAX

Propagation Delays (Note 6)

Data to Outputs

CD74FCT540 t

PLH

, t

PHL

5 6.4 2 8.5 ns

CD74FCT541 t

PLH

, t

PHL

5628ns

Output Disable to Output t

PLZ

, t

PHZ

5 7.1 2 9.5 ns

Output Enable to Output t

PZL

, t

PZH

5 7.5 2 10 ns

Power Dissipation Capacitance C

PD

(Note 7)

CD74FCT540 - 37 - - pF
CD74FCT541 - 40 - - pF

Minimum (Valley) V

OHV

During Switching of

Other Outputs (Output Under Test Not Switching)

V

OHV

5 0.5 - - V

Maximum (Peak) V

OLP

During Switching of

Other Outputs (Output Under Test Not Switching)

V

OLP

51- - V

Input Capacitance C

I

---10pF

Three-State Output Capacitance C

O

---15pF

NOTES:

6. 5V: Min is at 5.25V for 0oC to 70oC, Max is at 4.75V for 0oC to 70oC, Typ is at 5V.

7. CPD, measured per flip-flop, is used to determine the dynamic power consumption.
PD (per package) = VCC ICC + Σ(V

CC

2

fI CPD + V

O

2

fO CL + VCC∆ICC D) where:

VCC = supply voltage

∆ICC = flow through current x unit load

CL = output load capacitance

D = duty cycle of input high

fO = output frequency

fI = input frequency

CD74FCT540, CD74FCT541

8-5

CD74FCT540, CD74FCT541

8-6

Test Circuits and Waveforms

NOTE:

8. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; Z

OUT

≤ 50Ω;

tf, tr≤ 2.5ns.

FIGURE 1. TEST CIRCUIT

FIGURE 2. ENABLE AND DISABLE TIMING FIGURE 3. PROPAGATION DELAY

NOTES:

9. V

OLP

is measured with respect to a ground reference near the output under test. V

OHV

is measured with respect to VOH.

10. Input pulses have the following characteristics:
PRR≤ 1MHz, tr = 2.5ns, tf = 2.5ns, skew 1ns.

11. R.F. fixture with 700MHz design rules required. IC should be soldered into test board and bypassed with 0.1µF capacitor. Scope and
probes require 700MHz bandwidth.

FIGURE 4. SIMULTANEOUS SWITCHING TRANSIENT WAVEFORMS

3V

0

DUT

PULSE Z

O

GEN

7V

500Ω

50pF

500Ω

V

CC

R

T

RT = Z

O

V

0

C

L

R

L

R

L

V

I

tr, tf = 2.5ns

(NOTE 8)

SWITCH POSITION

TEST SWITCH

t

PLZ

, t

PZL

, Open Drain Closed

t

PHZ

, t

PZH

, t

PLH

, t

PHL

Open

DEFINITIONS:

C

L

= Load capacitance, includes jig and probe

capacitance.

RT= Terminationresistance, should be equal to Z

OUT

of

the Pulse Generator.

VIN = 0V to 3V.

Input: tr=tf= 2.5ns (10% to 90%), unless otherwise specified

3V

1.5V
0V

CONTROL INPUT

OUTPUT

NORMALLY LOW

OUTPUT

NORMALLY HIGH

SWITCH

OPEN

t

PZL

3.5V

1.5V

1.5V
0V

t

PLZ

t

PHZ

t

PZH

0V

3.5V

0.3V

0.3V

V

OL

V

OH

SWITCH

CLOSED

ENABLE DISABLE

1.5V

3V

0V

1.5V

3V

0V

t

PLH

SAME PHASE

INPUT TRANSITION

t

PHL

t

PLH

t

PHL

OPPOSITE PHASE

INPUT TRANSITION

OUTPUT

1.5V

V

OH

V

OL

OTHER
OUTPUTS

OUTPUT
UNDER
TEST

V

OH

V

OL

V

OH

V

OHV

V

OLP

V

OL

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