Texas Instruments CD74ACT297M Datasheet

D

Digital Design Avoids Analog
Compensation Errors

D

Easily Cascadable for Hlgher Order Loops

D

Useful Frequency Range
– DC to 110 MHz Typical (K CLK)
– DC to 70 MHz Typical (I/D CLK)

D

Dynamically Variable Bandwidth

D

Very Narrow Bandwidth Attainable

D

Power-On Reset

D

Output Capability
– Standand: XORPD OUT, ECPD OUT
– Bus Drlver: I/D OUT

D

SCR Latch-Up-Resistant CMOS Process
and Circuit Design

D

Speed of Bipolar FAST/AS/S with
Significantly Reduced Power Consumption

D

Balanced Propagation Delays

D

ESD Protectlon Exceeds 2000 V per
MIL-STD-883, Method 3015

D

Packaged in Small-Outline Integrated
Circuit Package

description

CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

M PACKAGE

(TOP VIEW)

ENCTR

K CLK

I/D CLK

D/U

I/D OUT

GND

B

1

A

2
3
4
5
6
7
8

V

16

CC

C

15

D

14

φA2

13

ECPD OUT

12

XORPD OUT

11

φB

10

9

φA1

The CD74ACT297 device is designed to provide a simple, cost-effective solution to high-accuracy, digital,
phase-locked-loop applications. These devices contain all the necessary circuits, with the exception of the
divide-by-N counter, to build first-order phase-locked loops as described in Figure 1.

Both exclusive-OR (XORPD) and edge-controlled (ECPD) phase detectors are provided for maximum flexibility .
Proper partitioning of the loop function, with many of the building blocks external to the package, makes it easy

for the designer to incorporate ripple cancellation or to cascade to higher order phase-locked loops.
The length of the up/down K counter is digitally programmable according to the K-counter function table. With

A, B, C, and D all low, the K counter is disabled. With A high and B, C, and D low, the K counter is only three
stages long, which widens the bandwidth or capture range and shortens the lock time of the loop. When A, B,
C, and D are programmed high, the K counter becomes 17 stages long, which narrows the bandwidth or capture
range and lengthens the lock time. Real-time control of loop bandwidth by manipulating the A-through-D inputs
can maximize the overall performance of the digital phase-locked loop.

This device performs the classic first-order phase-locked-loop function without using analog components. The
accuracy of the digital phase-locked loop (DPLL) is not affected by VCC and temperature variations, but depends
solely on accuracies of the K clock, I/D clock, and loop propagation delays. The I/D clock frequency and the
divide-by-N modulos determine the center frequency of the DPLL. The center frequency is defined by the
relationship f

= I/D clock/2N (Hz).

c

The CD74ACT297 is characterized for operation from –40°C to 85°C.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

TI is a trademark of Texas Instruments Incorporated.
FAST is a trademark of Fairchild Semiconductor.

PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Copyright  1999, Texas Instruments Incorporated

1

CD74ACT297
DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

Modulo Controls

DC B A

14 15 1 2

K CLK

D/U

ENCTR

I/D CLK

φA1

φB

φA2

10

13

4
6
3

5

9

Modulo K

Counter

J

K

Increment/Decrement

Circuit

7

I/D OUT

11

XORPD OUT

12

ECPD OUT

Figure 1. Simplifed Block Diagram

2

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

CD74ACT297

DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

Function Tables

K COUNTER

(DIGITAL CONTROL)

D

L L L L Inhibited
L L L H 2
L L H L 2
L L H H 2
L H L L 2
L H L H 2
L H H L 2

L H H H 2
H L L L 2
H L L H 2
H L H L 2
H L H H 21
H H L L 2
H H L H 2
H H H L 2
H H H H 2

C B A MODULO (K)

EXCLUSIVE-OR PHASE DETECTOR

φA1

L L L

L H H
H L H
H H L

φB XORPD OUT

3
4
5
6
7
8

9
10
11
12

3
14
15
16
17

EDGE-CONTROLLED PHASE DETECTOR

φA2

H or L ↓ H

↓ H or L L

H or L ↑ No change

↑ H or L No change

H = steady-state high level
L = steady-state low level

↓ = transition from high to low
↑ = transition from low to high

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

φB ECPD OUT

3

CD74ACT297
DIGITAL PHASE-LOCKED LOOP

SCHS297A – AUGUST 1998 – REVISED SEPTEMBER 1999

functional block diagram

K CLK

D/U

ENCTR

I/D CLK

2

A

1

B

15

C

14

D

4

6

3

POWER-UP RESET

l = 1

5

1
2
4
8

C20

20D

C20

20D

1

21D

C21

RR

T

T

TT

I/D Circuit

21D

C21

K Counter

X/Y

140

To Mode Controls 12–2 (11 stages not shown)

RR RR

14D

14T

M14

M14

14T

14D

21D

C21

13D

13T

M13

M13

13T

13D

78910111213

21D

C21

4635

1T

1T

RRRRR

Decrement

Increment

21J

C21

T

T

R

21

7

I/D OUT

φA1

φB

φA2

C21

21D

9

10

SS

13

C21

21D

Exclusive-OR Phase Detector

Edge-Controlled Phase Detector

RR

C21

21D

C21

21D

21K

11

XORPD OUT

12

ECPD OUT

4

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265