Texas Instruments CD74ACT283M, CD74ACT283E, CD74AC283M96, CD74AC283M, CD74AC283E Datasheet

Data sheet acquired from Harris Semiconductor
SCHS251D

CD54/74AC283,

CD54/74ACT283

August 1998 - Revised May 2000

Features

• Buffered Inputs

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

4-Bit Binary Fill Adder With Fast Carry

Description

The ’AC283 and ’ACT283 4-bit binary adders with fast carry
that utilize Advanced CMOS Logic technology. These
devices add two 4-bit binary numbers and generate a carry­out bit if the sum exceeds 15.

Because of the symmetry of the add function, this device
can be used with either all active-HIGH operands (positive
logic) or with all active-LOW operands (negative logic).
When using positive logic, the carry-in input must be tied
LOW if there is no carry-in.

Ordering Information

PART

NUMBER

CD54AC283F3A -55 to 125 16 Ld CERDIP
CD74AC283E 0 to 70oC, -40 to 85,

CD74AC283M 0 to 70oC, -40 to 85,

CD54ACT283F3A -55 to 125 16 Ld CERDIP
CD74ACT283E 0 to 70oC, -40 to 85,

CD74ACT283M 0 to 70oC, -40 to 85,

NOTES:

1. When ordering, use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waf erand die for this part number is available which meets all
electrical specifications. Please contact your local TI sales office or
customer service for ordering information.

TEMP.

RANGE (oC) PACKAGE

16 Ld PDIP

-55 to 125
16 Ld SOIC

-55 to 125

16 Ld PDIP

-55 to 125
16 Ld SOIC

-55 to 125

Pinout

CD54AC283, CD54ACT283

(CERDIP)

CD74AC283, CD74ACT283

(PDIP, SOIC)

TOP VIEW

16

1

S1

2

B1

3

A1

4

S0

5

A0

6

B0

7

C

IN

8

GND

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

V

CC

15

B2

14

A2

13

S2

12

A3
B3

11
10

S3

9

C

OUT

Functional Diagram

5

A0

6

B0

3

A1

2

B1

14

A2

15

B2

12

A3

11

B3

7

C

IN

1

4

S0

1

S1

13

S2

10

S3

C

OUT

GND = 8

= 16

V

CC

9

CD54/74AC283, CD54/74ACT283

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

IK

OK

CC orIGND

O

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. The package thermal impedance is calculated in accordance with JESD 51.

Thermal Impedance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

High Level Input Voltage V

Low Level Input Voltage V

High Level Output Voltage V

IH

IL

OH

TEST

CONDITIONS

- - 1.5 1.2 - 1.2 - 1.2 - V

- - 1.5 - 0.3 - 0.3 - 0.3 V

VIH or V

-0.05 1.5 1.4 - 1.4 - 1.4 - V

IL

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

-50

(Note 6, 7)

V

CC

(V)

3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

5.5 - - 3.85 - - - V

5.5----3.85 - V

25oC

-40oC TO
85oC

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

2

CD54/74AC283, CD54/74ACT283

DC Electrical Specifications (Continued)

-40oC TO
85oC

PARAMETER SYMBOL

Low Level Output Voltage V

OL

CONDITIONS

VIH or V

TEST

V

CC

25oC

(V)

0.05 1.5 - 0.1 - 0.1 - 0.1 V

IL

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

I

CC

VCC or

GND

0 5.5 - 8 - 80 - 160 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

2-2-2-V

5.5

Low Level Input Voltage V

IL

- - 4.5 to

- 0.8 - 0.8 - 0.8 V

5.5

High Level Output Voltage V

OH

VIH or V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

IL

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 6, 7)

-50

5.5----3.85 - V

(Note 6, 7)

Low Level Output Voltage V

OL

VIH or V

0.05 4.5 - 0.1 - 0.1 - 0.1 V

IL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 6, 7)

50

5.5-----1.65 V

(Note 6, 7)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1 µA

GND

Quiescent Supply Current
MSI

AdditionalSupply Currentper
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 8 - 80 - 160 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

6. Test one output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85oC, 75Ω at 125oC.

-55oC TO
125oC

UNITSVI(V) IO(mA) MIN MAX MIN MAX MIN MAX

ACT Input Load Table

INPUT UNIT LOAD

A0, B0, A2, B2 1.66

A1, B1 1.9
A3, B3 1.4

C

IN

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

1.1

3

CD54/74AC283, CD54/74ACT283

Switching Specifications Input t

, tf = 3ns, CL= 50pF (Worst Case)

r

-40oC TO 85oC -55oC TO 125oC

PARAMETER SYMBOL VCC (V)

AC TYPES

Propagation Delay,
An or Bn to C

OUT

CIN to Sn
CIN to C

OUT

t

PLH

, t

PHL

1.5 - - 199 - - 219 ns

3.3

6.3 - 22.4 6.2 - 24.6 ns

(Note 9)

5

4.5 - 16 4.4 - 17.6 ns

(Note 10)

Propagation Delay,
An or Bn to Sn

t

PLH

, t

PHL

1.5 - - 207 - - 228 ns

3.3 6.6 - 23.2 6.4 - 25.5 ns
5 4.7 - 16.5 4.6 - 18.2 ns

Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 120 - - 120 - pF

(Note 11)

ACT TYPES

Propagation Delay,
An or Bn to C

OUT

t

PLH

, t

PHL

5

4.5 - 16 2.7 - 17.6 ns

(Note 10)
CIN to Sn
CIN to C

OUT

Propagation Delay,

t

PLH

, t

PHL

5 4.7 - 16.5 3.3 - 18.2 ns

An or Bn to Sn
Input Capacitance C
Power Dissipation Capacitance C

I

PD

- - -10- -10pF

- - 120 - - 120 - pF

(Note 11)

NOTES:

8. Limits tested 100%.

9. 3.3V Min is at 3.6V, Max is at 3V.

10. 5V Min is at 5.5V, Max is at 4.5V.

11. CPD is used to determine the dynamic power consumption per function.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

UNITSMIN TYP MAX MIN TYP MAX

tr≤ 3ns tf≤ 3ns

INPUT

INVERTING

OUTPUT

t

PHL

FIGURE 1. PROPAGATION DELAY TIMES

t

PLH

INPUT LEVEL

90%
V

S

10%

GND

V

S

OUTPUT

R

(NOTE)

L

DUT

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

AC ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 2. PROPAGATION DELAY TIMES

4

3V

1.5V

0.5 V

CC

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Copyright  2000, Texas Instruments Incorporated