Texas Instruments CD74ACT14M96, CD74ACT14M, CD74ACT14E, CD74AC14E, CD74AC14M96 Datasheet

CD74AC14,

[ /Title
(CD74
AC14,
CD74
ACT14
)
/Sub­ject
(Hex
Invert­ing
Schmit
t Trig­ger)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)

Data sheet acquired from Harris Semiconductor
SCHS228

September 1998

Features

• Operates with Much Slower than Standard Input Rise
and Fall Slew Rates

• Exceptionally High Noise Immunity

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

• Greater Noise Immunity Than Standard Inverters

Pinout

CD74AC14, CD74ACT14

(PDIP, SOIC)

TOP VIEW

1A
1Y
2A
2Y
3A
3Y

GND

1
2
3
4
5
6
7

14

V

CC

6A

13
12

6Y

11

5A

10

5y

9

4A

8

4Y

CD74ACT14

Hex Inverting Schmitt Trigger

Description

The CD74AC14 and CD74ACT14 each contain six in v erting
Schmitt Triggers in one package. These devices use the Harris
Advanced CMOS Logic technology.

Ordering Information

PART

NUMBER

CD74AC14 -55 to 125 14 Ld PDIP E14.3
CD74ACT14 -55 to 125 14 Ld PDIP E14.3
CD74AC14 -55 to 125 14 Ld SOIC M14.15
CD74ACT14 -55 to 125 14 Ld SOIC M14.15

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waf eranddie for this part number isavailablewhich meets all elec­trical specifications.Please contact your local sales office or Harris
customer service for ordering information.

Functional Diagram

1A

2A

3A

4A

5A

6A

INPUTS OUTPUTS

AY

LH

HL

TEMP.

RANGE (oC) PACKAGE

1

3

5

9

11

13

TRUTH TABLE

2

1Y

4

2Y

6

3Y

8

4Y

10

5Y

12

6Y
GND = 7
V

= 14

CC

PKG.

NO.

FIGURE 1. HYSTERESIS DEFINITION AND CHARACTERISTIC

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

1

File Number 1984.1

CD74AC14, CD74ACT14

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

Input Rise and Fall Slew Rate, dt/dv (Note 6)

AC Types, 1.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 150ms (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

6. 5 Outputs switching: VCC = 5V; Load = 500Ω, 50pF; TA = Full Temperature Range
For AC, VI = 5.5V sawtooth; ACT, VI = 3V sawtooth.

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CC

DC Electrical Specifications

PARAMETER SYMBOL

AC TYPES

Positive-Going Threshold
Voltage

Negative-Going Threshold
Voltage

Hysteresis Voltage V
High Level Output Voltage V

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

V

+ - - 5 2.6 3.4 2.6 3.4 2.6 3.4 V

T

V

- - - 5 1.6 2.4 1.6 2.4 1.6 2.4 V

T

H

OH

- - 5 0.5 - 0.5 - 0.5 - V

VT+ or VT- -0.05 1.5 1.4 - 1.4 - 1.4 - V

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 7, 8)

-50

5.5----3.85 - V

(Note 7, 8)

UNITSV

2

CD74AC14, CD74ACT14

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

Low Level Output Voltage V

TEST

CONDITIONS

(V) IO(mA) MIN MAX MIN MAX MIN MAX

I

VT+ or VT- 0.05 1.5 - 0.1 - 0.1 - 0.1 V

OL

V

CC

(V)

25

o

C

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 7, 8)

50

5.5-----1.65 V

(Note 7, 8)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current,
SSI

I

CC

VCC or

0 5.5 - 4 - 40 - 80 µA

GND

ACT TYPES

Positive-Going Threshold
Voltage

Negative-Going Threshold
Voltage

Hysteresis Voltage V
High Level Output Voltage V

V

+ - - 5 1.4 2 1.4 2 1.4 2 V

T

V

- - - 5 0.8 1.3 0.8 1.3 0.8 1.3 V

T

H

OH

- - 5 0.4 - 0.4 - 0.4 - V

VT+ or VT- -0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

5.5 - - 3.85 - - - V

(Note 7, 8)

-50

5.5----3.85 - V

(Note 7, 8)

Low Level Output Voltage V

VT+ or VT- 0.05 4.5 - 0.1 - 0.1 - 0.1 V

OL

24 4.5 - 0.36 - 0.44 - 0.5 V
75

5.5 - - - 1.65 - - V

(Note 7, 8)

50

5.5-----1.65 V

(Note 7, 8)

Input Leakage Current I

I

VCC or

- 5.5 - ±0.1 - ±1-±1µA

GND

Quiescent Supply Current,
SSI

AdditionalSupplyCurrentper
Input Pin TTL Inputs High

I

CC

VCC or

0 5.5 - 4 - 40 - 80 µA

GND

∆I

CC

V

-2.1

CC

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

1 Unit Load

NOTES:

7. Test one output at a time fora 1-second maximumduration. Measurement is made by forcing currentand measuring voltageto minimize
power dissipation.

8. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

-40oC TO
85oC

-55oC TO
125oC

UNITSV

ACT Input Load Table

INPUT UNIT LOAD

All 0.21

NOTE: Unit load is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

3

CD74AC14, CD74ACT14

Switching Specifications Input t

PARAMETER SYMBOL V

, tf = 3ns, CL= 50pF (Worst Case)

r

(V)

CC

AC TYPES

Propagation Delay, Input to
Output

Input Capacitance C
Power Dissipation Capacitance C

t

PLH

, t

PD

I

PHL

5

2.7 - 9.5 2.6 - 10.5 ns

(Note 10)

- - -10- -10pF

- - 45 - - 45 - pF

(Note 11)

ACT TYPES

Propagation Delay, Input to
Output

Input Capacitance C
Power Dissipation Capacitance C

t

t

PLH

PHL

PD

5

(Note 10)

I

- - -10- -10pF

3.7 - 13.2 3.6 - 14.5 ns

2.4 - 8.6 2.4 - 9.5

- - 45 - - 45 - pF

(Note 11)

NOTES:

9. Limits tested at 100%.

10. 5V Min at 5.5V, Max at 4.5V.

11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = V
ACT: PD = V

2

fi(CPD + CL)

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

CC

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

OUTPUT

R

(NOTE)

L

C

L

50pF

500Ω

DUT

OUTPUT

LOAD

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

CD74AC CD74ACT

Input Level V
Input Switching Voltage, V
Output Switching Voltage, V

S

S

0.5 V

0.5 V

CC

CC
CC

FIGURE 2. PROPAGATION DELAY TIMES

3V

1.5V

0.5 V

CC

GND

tr = 3ns

LEVEL

V

I

V

O

INPUT

t

PHL

t

PLH

FIGURE 3.

t

= 3ns

f

90%
V

S

10%

V

S

GND

4

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