Datasheet CD74ACT08M96, CD74ACT08M, CD74ACT08E, CD74AC08M96, CD74AC08E Datasheet (Texas Instruments)

1

Data sheet acquired from Harris Semiconductor
SCHS226A

Features

• Buffered Inputs

• Typical Propagation Delay

- 4.3ns at V

CC

= 5V, TA = 25oC, CL = 50pF

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Description

The ’AC08 and ’ACT08 are quad 2-input AND gates that utiliz e
Advanced CMOS Logic technology.

Pinout

CD54AC08, CD54ACT08

(CERDIP)

CD74AC08, CD74ACT08

(PDIP, SOIC)

TOP VIEW

Functional Diagram

Ordering Information

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE

CD54AC08F3A -55 to 125 14 Ld CERDIP
CD74AC08E -55 to 125 14 Ld PDIP
CD74AC08M -55 to 125 14 Ld SOIC
CD54ACT08F3A -55 to 125 14 Ld CERDIP
CD74ACT08M -55 to 125 14 Ld SOIC

NOTES:

1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Waf eranddie for this partnumberis availablewhich meets all elec­trical specifications. Please contact yourTI local sales officeor cus­tomer service for ordering information.

1A
1B
1Y
2A
2B
2Y

GND

V

CC

4B
4A
4Y
3B
3A
3Y

1
2
3
4
5
6
7

14
13
12
11
10

9
8

TRUTH TABLE

INPUTS OUTPUTS

nA nB nY

LLL
HLL
LHL
HHH

1A

1B

2A

2B

2Y

GND

1

2

3

4

5

6

14

13

12

11

V

CC

4Y

3Y

3B

4A

4B

10

8

7

9

3A

1Y

September 1998 - Revised May 2000

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© 2000, Texas Instruments Incorporated

CD54/74AC08,

CD54/74ACT08

Quad 2-Input AND Gate

[ /Title
(CD74
AC08,
CD74
ACT08
)
/Sub­ject
(Quad
2-Input
AND
Gate)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan
ced
TTL)
/Cre­ator ()

2

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add ±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

AC TYPES

High Level Input Voltage V

IH

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

Low Level Input Voltage V

IL

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 1.5 1.4 - 1.4 - 1.4 - V

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

CD54/74AC08, CD54/74ACT08

3

Low Level Output Voltage V

OL

VIH or V

IL

0.05 1.5 - 0.1 - 0.1 - 0.1 V

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1 µA

Quiescent Supply Current,
SSI

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

5.5

2-2-2-V

Low Level Input Voltage V

IL

- - 4.5 to

5.5

- 0.8 - 0.8 - 0.8 V

High Level Output Voltage V

OH

VIH or V

IL

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75 5.5 - - 3.85 - - - V

-505.5----3.85 - V

Low Level Output Voltage V

OL

VIH or V

IL

0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1 µA

Quiescent Supply Current,
SSI

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load

∆I

CC

V

CC

-2.1

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

NOTES:

6. Test one output ata time for a 1-second maximum duration. Measurement is made byforcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

ACT Input Load Table

INPUT UNIT LOAD

All 0.3

NOTE: Unit load is ∆ICClimit specified in DCElectrical Specifications
Table, e.g., 2.4mA max at 25oC.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

CD54/74AC08, CD54/74ACT08

4

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case)

PARAMETER SYMBOL VCC (V)

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

AC TYPES

Propagation Delay, Input to
Output

t

PLH

, t

PHL

1.5 - - 99 - - 109 ns

3.3

(Note 9)

3.1 - 11.1 3.1 - 12.2 ns

5

(Note 10)

2.2 - 7.9 2.2 - 8.7 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 50 - - 50 - pF

ACT TYPES

Propagation Delay, Input to
Output

t

PLH

, t

PHL

5

(Note 10)

3.3 - 11.7 3.2 - 12.9 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 50 - - 50 - pF

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V.

11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = V

CC

2

fi(CPD + CL)

ACT: PD = V

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

DUT

OUTPUT

R

L

(NOTE)

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 1. PROPAGATION DELAY TIMES

AC ACT

Input Level V

CC

3V

Input Switching Voltage, V

S

0.5 V

CC

1.5V

Output Switching Voltage, V

S

0.5 V

CC

0.5 V

CC

FIGURE 2.

tr = 3ns

INPUT LEVEL

V

I

V

O

t

PLH

90%
V

S

10%

t

PHL

tf = 3ns

V

S

CD54/74AC08, CD54/74ACT08

IMPORTANT NOTICE

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pertaining to warranty, patent infringement, and limitation of liability.

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accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
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Copyright  2000, Texas Instruments Incorporated