• SCR-Latchup-Resistant CMOS Process and Circuit
Design
• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption
• Balanced Propagation Delays
• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply
• ±24mA Output Drive Current
- Fanout to 15 FAST™ ICs
- Drives 50Ω Transmission Lines
Description
The ’AC08 and ’ACT08 are quad 2-input AND gates that utiliz e
Advanced CMOS Logic technology.
Pinout
CD54AC08, CD54ACT08
(CERDIP)
CD74AC08, CD74ACT08
(PDIP, SOIC)
TOP VIEW
Functional Diagram
Ordering Information
PART
NUMBER
TEMP.
RANGE (oC)PACKAGE
CD54AC08F3A-55 to 12514 Ld CERDIP
CD74AC08E-55 to 12514 Ld PDIP
CD74AC08M-55 to 12514 Ld SOIC
CD54ACT08F3A-55 to 12514 Ld CERDIP
CD74ACT08M-55 to 12514 Ld SOIC
NOTES:
1. When ordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.
2. Waf eranddie for this partnumberis availablewhich meets all electrical specifications. Please contact yourTI local sales officeor customer service for ordering information.
1A
1B
1Y
2A
2B
2Y
GND
V
CC
4B
4A
4Y
3B
3A
3Y
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TRUTH TABLE
INPUTSOUTPUTS
nAnBnY
LLL
HLL
LHL
HHH
1A
1B
2A
2B
2Y
GND
1
2
3
4
5
6
14
13
12
11
V
CC
4Y
3Y
3B
4A
4B
10
8
7
9
3A
1Y
September 1998 - Revised May 2000
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
3. For up to 4 outputs per device, add ±25mA for each additional output.
4. Unless otherwise specified, all voltages are referenced to ground.
5. θJA is measured with the component mounted on an evaluation PC board in free air.
AdditionalSupplyCurrentper
Input Pin TTL Inputs High
1 Unit Load
∆I
CC
V
CC
-2.1
-4.5 to
5.5
-2.4-2.8-3mA
NOTES:
6. Test one output ata time for a 1-second maximum duration. Measurement is made byforcing current and measuring voltage to minimize
power dissipation.
7. Test verifies a minimum 50Ω transmission-line-drive capability at 85
o
C, 75Ω at 125oC.
ACT Input Load Table
INPUTUNIT LOAD
All0.3
NOTE: Unit load is ∆ICClimit specified in DCElectrical Specifications
Table, e.g., 2.4mA max at 25oC.
DC Electrical Specifications (Continued)
PARAMETERSYMBOL
TEST
CONDITIONS
V
CC
(V)
25
o
C
-40oC TO
85oC
-55oC TO
125oC
UNITSV
I
(V)IO(mA)MINMAXMINMAXMINMAX
CD54/74AC08, CD54/74ACT08
4
Switching Specifications Input t
r
, tf = 3ns, CL= 50pF (Worst Case)
PARAMETERSYMBOL VCC (V)
-40oC TO 85oC-55oC TO 125oC
UNITSMINTYPMAXMINTYPMAX
AC TYPES
Propagation Delay, Input to
Output
t
PLH
, t
PHL
1.5--99--109ns
3.3
(Note 9)
3.1-11.13.1-12.2ns
5
(Note 10)
2.2-7.92.2-8.7ns
Input CapacitanceC
I
-- -10- -10pF
Power Dissipation CapacitanceC
PD
(Note 11)
--50--50-pF
ACT TYPES
Propagation Delay, Input to
Output
t
PLH
, t
PHL
5
(Note 10)
3.3-11.73.2-12.9ns
Input CapacitanceC
I
-- -10- -10pF
Power Dissipation CapacitanceC
PD
(Note 11)
--50--50-pF
NOTES:
8. Limits tested at 100%.
9. 3.3V Min at 3.6V, Max at 3V.
10. 5V Min at 5.5V, Max at 4.5V.
11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = V
CC
2
fi(CPD + CL)
ACT: PD = V
CC
2
fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.
DUT
OUTPUT
R
L
(NOTE)
OUTPUT
LOAD
500Ω
C
L
50pF
NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.
FIGURE 1. PROPAGATION DELAY TIMES
ACACT
Input LevelV
CC
3V
Input Switching Voltage, V
S
0.5 V
CC
1.5V
Output Switching Voltage, V
S
0.5 V
CC
0.5 V
CC
FIGURE 2.
tr = 3ns
INPUT LEVEL
V
I
V
O
t
PLH
90%
V
S
10%
t
PHL
tf = 3ns
V
S
CD54/74AC08, CD54/74ACT08
IMPORTANT NOTICE
T exas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
Customers are responsible for their applications using TI components.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
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