Texas Instruments CD74ACT05M96, CD74ACT05M, CD74ACT04M96, CD74ACT04M, CD74ACT04E Datasheet

1

Data sheet acquired from Harris Semiconductor
SCHS225

Features

• CD74AC04, CD74ACT04 . . . . . . . . . . . . Active Outputs

• CD74AC05, CD74ACT05 . . . . . . . .Open-Drain Outputs

• Buffered Inputs

• Typical Propagation Delay

- 3.5ns at V

CC

= 5V, TA = 25oC, CL = 50pF

• Exceeds 2kV ESD Protection MIL-STD-883, Method
3015

• SCR-Latchup-Resistant CMOS Process and Circuit
Design

• Speed of Bipolar FAST™/AS/S with Significantly
Reduced Power Consumption

• Balanced Propagation Delays

• AC Types Feature 1.5V to 5.5V Operation and
Balanced Noise Immunity at 30% of the Supply

• ±24mA Output Drive Current

- Fanout to 15 FAST™ ICs

- Drives 50Ω Transmission Lines

Description

The CD74AC04, CD74ACT04, CD74AC05 and CD74ACT05
are hex inverters that utilize the Harris Advanced CMOS
Logic technology.

Pinout

CD74AC04, CD74ACT04, CD74AC05, CD74ACT05

(PDIP, SOIC)

TOP VIEW

Functional Diagram

Ordering Information

PART

NUMBER

TEMP.

RANGE (oC) PACKAGE

PKG.

NO.

CD74AC04E -55 to 125 14 Ld PDIP E14.3
CD74ACT04E -55 to 125 14 Ld PDIP E14.3
CD74AC05E -55 to 125 14 Ld PDIP E14.3
CD74ACT05E -55 to 125 14 Ld PDIP E14.3
CD74AC04M -55 to 125 14 Ld SOIC M14.15
CD74ACT04M -55 to 125 14 Ld SOIC M14.15
CD74AC05M -55 to 125 14 Ld SOIC M14.15
CD74ACT05M -55 to 125 14 Ld SOIC M14.15

NOTES:

1. Whenordering,use the entire part number. Add the suffix 96 to
obtain the variant in the tape and reel.

2. Wafer and die forthispart number is availablewhichmeetsallelec­trical specifications. Please contact your local sales office or Harris
customer service for ordering information.

1A
1Y
2A
2Y
3A
3Y

GND

V

CC

6A
6Y
5A
5Y
4A
4Y

1
2
3
4
5
6
7

14
13
12
11
10

9
8

TRUTH TABLE

CD74AC/ACT04 CD74AC/ACT05

INPUT OUTPUT INPUT OUTPUT

LHLZ
HLHL

Z = High Impedance

1A

2A

3A

4A

5A

6A

1

3

5

9

11

13

2

4

6

8

1Y

4Y

6Y

GND = 7
V

CC

= 14

5Y

3Y

2Y

10

12

September 1998

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
FAST™ is a Trademark of Fairchild Semiconductor.

Copyright

© Harris Corporation 1998

CD74A C04, CD74ACT04,

CD74A C05, CD74ACT05

Hex Inverters

File Number 1945.1

[ /Title
(CD74
AC04,
CD74
ACT04
,
CD74
AC05,
CD74
ACT05
)
/Sub­ject
(Hex
Invert­ers)
/Autho
r ()
/Key­words
(Har­ris
Semi­con­ductor,
Advan
ced
CMOS
,Harris
Semi­con­ductor,
Advan

2

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC. . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 6V

DC Input Diode Current, I

IK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, I

OK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC Output Source or Sink Current per Output Pin, I

O

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±50mA

DC VCC or Ground Current, I

CC orIGND

(Note 3) . . . . . . . . .±100mA

Operating Conditions

Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC (Note 4)

AC Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1.5V to 5.5V

ACT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to V

CC

Input Rise and Fall Slew Rate, dt/dv

AC Types, 1.5V to 3V . . . . . . . . . . . . . . . . . . . . . . . . . 50ns (Max)

AC Types, 3.6V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . . 20ns (Max)

ACT Types, 4.5V to 5.5V. . . . . . . . . . . . . . . . . . . . . . . 10ns (Max)

Thermal Resistance (Typical, Note 5) θJA (oC/W)

PDIP Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

SOIC Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175

Maximum Junction Temperature (Plastic Package) . . . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTES:

3. For up to 4 outputs per device, add±25mA for each additional output.

4. Unless otherwise specified, all voltages are referenced to ground.

5. θJA is measured with the component mounted on an evaluation PC board in free air.

DC Electrical Specifications

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

AC TYPES

High Level Input Voltage V

IH

- - 1.5 1.2 - 1.2 - 1.2 - V
3 2.1 - 2.1 - 2.1 - V

5.5 3.85 - 3.85 - 3.85 - V

Low Level Input Voltage V

IL

- - 1.5 - 0.3 - 0.3 - 0.3 V
3 - 0.9 - 0.9 - 0.9 V

5.5 - 1.65 - 1.65 - 1.65 V

High Level Output Voltage
(04)

V

OH

VIH or V

IL

-0.05 1.5 1.4 - 1.4 - 1.4 - V

-0.05 3 2.9 - 2.9 - 2.9 - V

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-4 3 2.58 - 2.48 - 2.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75

(Note 6, 7)

5.5 - - 3.85 - - - V

-50

(Note 6, 7)

5.5----3.85 - V

CD74AC04, CD74ACT04, CD74AC05, CD74ACT05

3

Low Level Output Voltage V

OL

VIH or V

IL

0.05 1.5 - 0.1 - 0.1 - 0.1 V

0.05 3 - 0.1 - 0.1 - 0.1 V

0.05 4.5 - 0.1 - 0.1 - 0.1 V
12 3 - 0.36 - 0.44 - 0.5 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Supply Current,
SSI

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

ACT TYPES

High Level Input Voltage V

IH

- - 4.5 to

5.5

2-2-2-V

Low Level Input Voltage V

IL

- - 4.5 to

5.5

- 0.8 - 0.8 - 0.8 V

High Level Output Voltage
(04)

V

OH

VIH or V

IL

-0.05 4.5 4.4 - 4.4 - 4.4 - V

-24 4.5 3.94 - 3.8 - 3.7 - V

-75 5.5 - - 3.85 - - - V

-505.5----3.85 - V

Low Level Output Voltage V

OL

VIH or V

IL

0.05 4.5 - 0.1 - 0.1 - 0.1 V
24 4.5 - 0.36 - 0.44 - 0.5 V
75

(Note 6, 7)

5.5 - - - 1.65 - - V

50

(Note 6, 7)

5.5-----1.65 V

Input Leakage Current I

I

VCC or

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Supply Current,
SSI

I

CC

VCC or

GND

0 5.5 - 4 - 40 - 80 µA

AdditionalSupply Current per
Input Pin TTL Inputs High
1 Unit Load

∆I

CC

V

CC

-2.1

- 4.5 to

5.5

- 2.4 - 2.8 - 3 mA

NOTES:

6. Testone output at a time for a 1-second maximum duration. Measurement is made by forcing current and measuring voltage to minimize
power dissipation.

7. Test verifies a minimum 50Ω transmission-line-drive capability at 85

o

C, 75Ω at 125oC.

ACT Input Load Table

INPUT UNIT LOAD

nA 0.18

NOTE: Unitload is ∆ICClimit specified in DC Electrical Specifications
Table, e.g., 2.4mA max at 25oC.

DC Electrical Specifications (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

V

CC

(V)

25

o

C

-40oC TO
85oC

-55oC TO
125oC

UNITSV

I

(V) IO(mA) MIN MAX MIN MAX MIN MAX

CD74AC04, CD74ACT04, CD74AC05, CD74ACT05

4

Switching Specifications Input t

r

, tf = 3ns, CL= 50pF (Worst Case)

PARAMETER SYMBOL V

CC

(V)

-40oC TO 85oC -55oC TO 125oC
UNITSMIN TYP MAX MIN TYP MAX

AC TYPES

Propagation Delay, Input to
Output (CD74AC/ACT04)

t

PLH

, t

PHL

1.5 - - 74 - - 81 ns

3.3

(Note 9)

2.3 - 8.3 2.3 - 9.1 ns

5

(Note 10)

1.7 - 5.9 1.6 - 6.5 ns

Propagation Delay, High Z to
Output Low (CD74AC/ACT05)

t

PZL

1.5 - - 74 - - 81 ns

3.3 2.3 - 8.3 2.3 - 9.1 ns
5 1.7 - 5.9 1.6 - 6.5 ns

Propagation Delay, Output Low
to High Z (CD74AC/ACT05)

t

PLZ

1.5 - - 94 - - 103 ns

3.3 3 - 10.4 2.9 - 11.5 ns
5 2.2 - 7.5 2.1 - 8.2 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 105 - - 105 - pF

ACT TYPES

Propagation Delay, Input to
Output (CD74AC/ACT04)

t

PLH

, t

PHL

5

(Note 10)

2.4 - 8.5 2.3 - 9.3 ns

Propagation Delay, Output Low
to High Z

t

PLZ

5 2.8 - 9.8 2.7 - 10.8 ns

Propagation Delay, High Z to
Output Low (CD74AC/ACT05)

t

PZL

5 2.4 - 8.5 2.3 - 9.3 ns

Input Capacitance C

I

- - -10- -10pF

Power Dissipation Capacitance C

PD

(Note 11)

- - 105 - - 105 - pF

NOTES:

8. Limits tested at 100%.

9. 3.3V Min at 3.6V, Max at 3V.

10. 5V Min at 5.5V, Max at 4.5V.

11. CPD is used to determine the dynamic power consumption per gate.
AC: PD = V

CC

2

fi(CPD + CL)

ACT: PD = V

CC

2

fi(CPD + CL) + VCC∆ICC where fi = input frequency, CL = output load capacitance, VCC = supply voltage.

DUT

OUTPUT

R

L

(NOTE)

OUTPUT

LOAD

500Ω

C

L

50pF

NOTE: For AC Series Only: When VCC = 1.5V, RL = 1kΩ.

FIGURE 1. PROPAGATION DELAY TIMES

CD74AC CD74ACT

Input Level V

CC

3V

Input Switching Voltage, V

S

0.5 V

CC

1.5V

Output Switching Voltage, V

S

0.5 V

CC

0.5 V

CC

FIGURE 2. WAVEFORMS

INPUT

t

r

t

f

90%
V

S

GND

OUTPUT

t

PHL

t

PLH

V

S

CD74AC04, CD74ACT04, CD74AC05, CD74ACT05

5

FIGURE 3. PROPAGATION DELAY TIMES AND TEST CIRCUIT

INPUT LEVEL

V

S

t

PZL

nA

t

PLZ

nY

20%

OUTPUT

LOW

OUTPUT

OFF

OUTPUT

LOW

500Ω

50pF

V

CC

nA

500Ω

V

S

V

S

CD74AC04, CD74ACT04, CD74AC05, CD74ACT05

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